KR950002185B1 - Semiconductor device with shallow junction phenomenon and manufacturing method - Google Patents
Semiconductor device with shallow junction phenomenon and manufacturing method Download PDFInfo
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- KR950002185B1 KR950002185B1 KR1019910022950A KR910022950A KR950002185B1 KR 950002185 B1 KR950002185 B1 KR 950002185B1 KR 1019910022950 A KR1019910022950 A KR 1019910022950A KR 910022950 A KR910022950 A KR 910022950A KR 950002185 B1 KR950002185 B1 KR 950002185B1
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- 239000004065 semiconductor Substances 0.000 title claims description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 14
- 238000005468 ion implantation Methods 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 239000006185 dispersion Substances 0.000 claims 1
- 238000000926 separation method Methods 0.000 claims 1
- 150000002500 ions Chemical class 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 229910015900 BF3 Inorganic materials 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron fluoride ions Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0151—Manufacturing their isolation regions
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- General Physics & Mathematics (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
Abstract
내용 없음.No content.
Description
제 1 도는 본 발명에 따라 Si이 먼저 이온주입된 상태를 나타낸 반도체소자의 단면도.1 is a cross-sectional view of a semiconductor device showing a state in which Si is first implanted according to the present invention.
제 2 도는 본 발명에 따라 제 1 도의 공정 다음에 BF2이 주입된 상태를 나타낸 반도체소자의 단면도.2 is a cross-sectional view of a semiconductor device showing a state in which BF 2 is implanted after the process of FIG. 1 according to the present invention.
제 3 도는 본 발명에 따라 P+얕은 접합이 형성된 상태를 나타내는 반도체소자의 단면도.3 is a cross-sectional view of a semiconductor device showing a state in which a P + shallow junction is formed in accordance with the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : P-형 실리콘 기판 2 : n-영역1: P - type silicon substrate 2: n - region
3 : 소자분리산화막 4 : 스크린 산화막3: device isolation oxide film 4: screen oxide film
5 : P+영역 6 : 도전층5: P + region 6: conductive layer
7 : 포토레지스트층7: photoresist layer
본 발명은 고집적 반도체 기억소자에 적용될 수 있는 얕은 접합 형상을 가진 반도체소자 및 그 제조방법에 관한 것으로, 특히, 실리콘기판이 선 비정질화되어 P+형의 얕은 접합형상을 가지게 되는 반도체소자 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a shallow junction shape that can be applied to a highly integrated semiconductor memory device and a method of manufacturing the same. In particular, a semiconductor device in which a silicon substrate is pre-amorphized to have a shallow junction shape of P + type and its fabrication It is about a method.
최근, 반도체소자가 고집적화가 됨에 따라, 트랜지스터가 미세화되므로, 채널길이가 짧게 되는 단채널효과를 가지게 되어, 펀치스쿠(punch through)현상이 발생하게 된다.In recent years, as semiconductor devices have been highly integrated, transistors have been miniaturized, so that the channel length has a short channel effect, and punch through phenomenon occurs.
따라서, 상기 단채널효과를 경감시키기 위해, 종래의 기술에 있어서는, P+실리콘기판 상부에 소정의 n_액티브영역을 형성한 다음 리소그래피기술에 의해 선택적으로 불화붕소이온을 예를 들어, 3×1015/㎠정도 상기 n_액티브영역에 주입하고, 그 질소분위기에서 900℃ 30분간 열처리하여, 주입된 이온을 전기적으로 활성화시켜 P+영역을 형성하고 그 상부에 알루미늄패트와 같은 도전층을 증착시켜 얕은 접합을 가진 다이오드를 제조하였다.Therefore, in order to alleviate the short channel effect, in the related art, a predetermined n_ active region is formed on the P + silicon substrate, and then boron fluoride ion is selectively selected by lithography, for example, 3x10. 15 / cm 2 injected into the n_ active region and heat-treated at 900 DEG C for 30 minutes in the nitrogen atmosphere to electrically activate the implanted ions to form a P + region and to deposit a conductive layer such as aluminum pat on top of it. Diodes with shallow junctions were made.
그러나, 상술한 종래의 기술에 있어서는 리소그래피기술에 의해 선택적으로 단결정 실리콘기판상으로 주입되는 불화붕소이온이 실리콘 단결정에서의 열린 통로를 따라 깊숙이 들어가는 현상을 나타낸다.However, the conventional technique described above shows a phenomenon in which boron fluoride ions, which are selectively implanted onto a single crystal silicon substrate by lithography, enter deeply along an open passage in the silicon single crystal.
따라서, 본 발명은, 면적이 예로서 200×400㎛2인 소정의 n_영역에 리소그래피기술에 의해 선택적으로 예로서, Si 이온을 40kev의 에너지와 1015/㎠의 양으로 먼저 주입시켜 실리콘 단결정의 규칙성을 파괴하여, 뒤따르는 공정인 불화붕소이온의 주입공정에 의해 발생되는 실리콘기판 단결정에서의 열린 통로를 따라 깊숙이 들어가는 현상을 방지하여, P+영역의 붕소농도와 n_영역의 인농도가 같아져서 접합깊이가 0.2㎛이하인 P+영역의 얕은 접합의 다이오드를 형성하여 접합깊이 및 누설전류를 작게 하여 단채널효과를 억제하는 것을 그 목적으로 한다.Accordingly, the present invention provides a surface area for example, to a selective region on a predetermined n _ 2 × 200 400㎛ for example by a lithographic method, a silicon single crystal by first implanting Si ions in an amount of energy and 10 15 / ㎠ 40kev The boron concentration in the P + region and the phosphorus concentration in the n _ region are prevented by breaking the regularity of and preventing the deep penetration along the open passage in the silicon substrate single crystal generated by the subsequent implantation process of boron fluoride ion. The purpose is to suppress the short channel effect by forming a diode of a shallow junction in the P + region where the junction depth is equal to or smaller than 0.2 μm, thereby reducing the junction depth and leakage current.
따라서, 본 발명에 의한 얕은 접합형상을 가진 반도체소자 제조방법에 있어서, P_타입의 실리콘기판을 제공하는 단계와, 상기 기판 상부에 n_영역을 형성하는 단계와, 상기 n_영역 상부에 소자분리 산화막을 형성하는 단계와, 상기 소자분리 산화막 상부에 스크린 산화막을 형성하는 단계와, 상기 스크린 산화막 상부의 소정부분에 포토레지스트층을 형성하는 단계와, 노출된 상기 스크린 산화막 상부로부터 Si를 n_영역의 소정부분에 이온주입시키는 단계와, 상기 Si가 이온주입된 n_영역의 소정부분에 BF2를 이온주입시키는 단계와, 상기 스크린 산화막 상부에 형성된 포토레지스트층을 제거하는 단계와, 열처리를 거쳐서 상기 BF2가 이온주입된 영역에 P+영역을 형성하는 단계와, 상기 스크린 산화막의 소정부분을 리소그래피기술을 이용하여 콘택홀을 형성하고, 그 상부에 도전층을 증착하는 단계를 포함하는 것을 특징으로 한다.Therefore, in the method of manufacturing a semiconductor device having a shallow junction shape according to the present invention, providing a P_ type silicon substrate, forming an n_ region on the substrate, and forming a device on the n_ region forming a separating oxide film, and a step of forming a screen oxide film in the device isolation oxide film above, and a step of forming a photoresist layer on a predetermined portion of the screen oxide layer upper and the Si from the exposed said screen oxide upper n _ and the step of ion implantation in a predetermined part of the region, the method comprising the step of the Si is ion-implanted BF 2 at a predetermined portion of the ion-implanted n _ region, removing the photoresist layer formed on an upper part of the screen oxide film, a thermal treatment Forming a P + region in the BF 2 ion implanted region, and forming a predetermined portion of the screen oxide layer using a lithography technique. Forming a tack hole, and depositing a conductive layer thereon.
또한, 본 발명에 의한 얕은 접합형상을 가진 반도체소자에 있어서, P_타입의 실리콘 기판과, 상기 기판에 형성된 n_영역과, 상기 n_영역 상부에 형성된 소자분리산화막과, 상기 소자분리 산화막 상부에 형성된 스크린 산화막과, 상기 n_영역의 소정 부분에 형성된 P+영역과, 상기 P+영역 상부의 콘택홀을 통하여 P+영역과 전기적으로 접속되는 모전층을 구비하는 것을 특징으로 한다.In addition, in the semiconductor device having a shallow junction shape according to the present invention, a P_ type silicon substrate, an n_ region formed on the substrate, a device isolation oxide film formed on the n_ region, and an upper portion of the device isolation oxide film through the screen oxide layer and a P + region and a contact hole in the upper part of the P + regions formed in the predetermined portion of the n _ region formed is characterized by having a mojeon layer is connected to a P + region and electrically.
또한, 본 발명에 의한 얇은 접합형상을 가진 반도체소자에 있어서, P+영역은, Si를 n_영역에 먼저 이온주입시켜 실리콘 기판을 선 비정질화 한 후 BF2를 이온주입시켜 형성되는 것을 특징으로 한다.In addition, in the semiconductor device having a thin junction shape according to the present invention, the P + region is formed by ion implantation of Si into the n _ region first to pre-amorphize the silicon substrate and then implantation of BF 2 into the ion region. do.
이하, 첨부된 도면으로 본 발명을 더욱 상세하게 설명하기로 한다.Hereinafter, the present invention will be described in detail with the accompanying drawings.
제 1 도는, P_타입의 실리콘기판 상부에 예로서 인을 1013/㎠, 150kev의 조건으로 주입하여 열처리하여 n_영역을 소정부분 형성시킨후, 그 상부에 LOCOS 공정으로 소자분리 산화막(3)을 형성시키고, 상기 소자분리 산화막(3)상부에 스크린 산화막(4)을 형성시키고, 상기 스크린 산화막(4) 상부의 소정부분에 포토레지스트층(7)을 형성시켜, Si 이온을 40kev, 1015/㎠ 조건으로 n_영역의 소정부분에 이온주입시키는 상태를 도시한다.The first turn, P _ type of the silicon substrate by the upper heat-treated by injecting the to 10 13 / ㎠, conditions of 150kev for example in then the n _ region forming a predetermined section, the element isolation by LOCOS process on the top oxide film (3 ), A screen oxide film 4 is formed on the device isolation oxide film 3, and a photoresist layer 7 is formed on a predetermined portion of the screen oxide film 4 to form Si ions of 40 kev, 10. to 15 / ㎠ condition shows a state in which the ion implantation to the predetermined portion of the n _ zone.
이때, 상기 Si 이온주입에 의해 실리콘기판의 단결정의 규칙성은 파괴되어 실리콘기판은 비정질화된다.At this time, the regularity of the single crystal of the silicon substrate is destroyed by the Si ion implantation, and the silicon substrate is amorphous.
제 2 도는 제 1 도에 도시된 공정 다음에, BF2이온을 3×1015㎠, 50kev의 조건으로 이온주입시키는 공정을 도시한 것이다.FIG. 2 shows a step of implanting BF 2 ions under the conditions of 3 × 10 15 cm 2 and 50 kev following the process shown in FIG. 1.
제 3 도는, 상기 BF2이온을 이온주입시킨후 잔존하는 포토레지스트층(7)을 제거하여, 600℃, 60분 및 900℃, 30분동안 질소분위기에서 열처리를 거쳐 P+영역(5)을 형성시키고, 그 상부에 리소그래피기술에 의해 형성된 콘택홀을 통해 알루미늄패드인 도전층(6)을 형성한 상태를 도시한 것이다.3, after the ion implantation of the BF 2 ions, the remaining photoresist layer 7 is removed, and the P + region 5 is subjected to heat treatment in a nitrogen atmosphere at 600 ° C., 60 minutes, and 900 ° C. for 30 minutes. The conductive layer 6, which is an aluminum pad, is formed through the contact hole formed by the lithographic technique.
이하, 표 1에서는, Si 이온주입을 이용하지 않는 종래기술에 의해 형성된 다이오드와, 본 발명에 의한 Si 이온주입기술을 이용하여 형성된 다이오드의 접합깊이 및 -5V를 인가하였을 때의 누설전류를 측정한 값을 비교하여 도시한다.Hereinafter, in Table 1, the junction depth of the diode formed by the prior art which does not use Si ion implantation and the diode formed by using the Si ion implantation technique according to the present invention and the leakage current when applying -5V were measured. The values are compared and shown.
[표 1]TABLE 1
여기서, 누설전류는 -5V를 도전층에 인가할때 다이오드면적 200×400㎛2를 통하여 흐르는 전류이다.Here, the leakage current is a current flowing through the diode area 200 x 400 탆 2 when -5 V is applied to the conductive layer.
표 1에서 알 수 있는 바와같이, 본 발명의 Si 이온주입을 이용한 기술이 종래의 기술에 비해 접합깊이와 누설전류의 특성에 있어서 매우 양호함을 알 수 있다.As can be seen from Table 1, it can be seen that the technique using the Si ion implantation of the present invention is very good in the characteristics of the junction depth and the leakage current compared to the conventional technique.
이상에 살펴본 바와같이, 본 발명에 따른 실리콘기판을 선비정절화하여 얕은 접합형상을 가진 반도체소자는, 접합깊이 및 누설전류를 작게함으로써 트랜지스터의 단채널효과를 경감시켜 소자의 고집적화에 크게 기여할 수 있는 효과를 가진다.As described above, the semiconductor device having a shallow junction shape by pre-ordering the silicon substrate according to the present invention can reduce the short channel effect of the transistor by reducing the junction depth and the leakage current, thereby greatly contributing to the high integration of the device. Has an effect.
Claims (5)
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| KR1019910022950A KR950002185B1 (en) | 1991-12-13 | 1991-12-13 | Semiconductor device with shallow junction phenomenon and manufacturing method |
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| Country | Link |
|---|---|
| KR (1) | KR950002185B1 (en) |
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1991
- 1991-12-13 KR KR1019910022950A patent/KR950002185B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR930014782A (en) | 1993-07-23 |
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