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KR940023196A - Image memory circuit for digital processing of interlaced video signals - Google Patents

Image memory circuit for digital processing of interlaced video signals Download PDF

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Publication number
KR940023196A
KR940023196A KR1019930005263A KR930005263A KR940023196A KR 940023196 A KR940023196 A KR 940023196A KR 1019930005263 A KR1019930005263 A KR 1019930005263A KR 930005263 A KR930005263 A KR 930005263A KR 940023196 A KR940023196 A KR 940023196A
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KR
South Korea
Prior art keywords
memory bank
memory
image
digital processing
memory circuit
Prior art date
Application number
KR1019930005263A
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Korean (ko)
Inventor
정석
Original Assignee
정석
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 정석 filed Critical 정석
Priority to KR1019930005263A priority Critical patent/KR940023196A/en
Publication of KR940023196A publication Critical patent/KR940023196A/en

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Abstract

본 발명은 비월주사방식 동화상신호의 확대, 축소, 기타 변형을 위한 디지탈 처리장치에 있어서의 화상메모리 회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image memory circuit in a digital processing apparatus for enlarging, reducing, or otherwise modifying interlaced video signals.

본 발명의 화상 메모리 회로는 아날로그 화상신호를 디지탈 신호로 변환하는 A/D 컨버터와 화상 데이타를 저장할 수 있는 메모리 뱅크, 디지탈 신호를 아날로그 화상신호로 변환하는 D/A컨버터로 구성되는 화상처리회로에 있어서 메모리 뱅크가 3개의 메모리 뱅크(2,3,4)로 구성되는 것을 특징으로 한다.The image memory circuit of the present invention comprises an A / D converter for converting an analog image signal into a digital signal, a memory bank for storing image data, and a D / A converter for converting a digital signal into an analog image signal. It is characterized in that the memory bank is composed of three memory banks (2, 3, 4).

Description

비월주사방식 동화상신호의 디지탈처리를 위한 화상메모리 회로Image memory circuit for digital processing of interlaced video signals

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 구성을 나타낸 도면, 제2도는 제1도에 따른 각 메모리 뱅크의 쓰기와 읽기 필드상태 표시도.1 is a diagram showing the configuration of the present invention, and FIG. 2 is a diagram showing write and read field states of each memory bank according to FIG.

Claims (2)

아날로그 화상신호를 디지탈 신호로 변환하는 A/D 컨버터와 화상 데이타를 저장할 수 있는 메모리 뱅크, 디지탈 신호를 아날로그 화상신호로 변환하는 D/A 컨버터로 구성되는 화상처리 회로에 있어서 메모리 뱅크가 3개의 메모리 뱅크(2,3,4)로 구성되는 것을 특징으로 하는 비월주사방식 동화상 신호의 디지탈 처리를 위한 화상메모리 회로.In an image processing circuit comprising an A / D converter for converting an analog image signal into a digital signal, a memory bank for storing image data, and a D / A converter for converting a digital signal into an analog image signal, the memory bank includes three memories. An image memory circuit for digital processing of interlaced scanning video signals, comprising banks (2, 3, 4). 한 필드주사시간 내에서 3개의 메모리 뱅크(2,3,4)중 하나에 화상 데이타가 쓰여지고 다른 2개의 메모리 뱅크로 완전한 1프레임 화상 데이타를 구성하여 출력하며 매 필드마다 쓰여지는 메모리 뱅크가 제1메모리 뱅크(2)에서 제2메모리 뱅크(3), 제2메모리 뱅크(3)에서 제3메모리 뱅크(4), 제3메모리 뱅크(4)에서 제1메모리 뱅크(2)로 바뀌는 비월주사방식 동화상 신호의 디지탈 처리를 위한 화상메모리 회로.The image data is written to one of the three memory banks (2, 3, 4) within one field scan time, and the complete two-frame image data is composed and output to the other two memory banks. Interlaced scanning scheme that changes from the memory bank 2 to the second memory bank 3, the second memory bank 3 to the third memory bank 4, and the third memory bank 4 to the first memory bank 2. An image memory circuit for digital processing of moving picture signals. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930005263A 1993-03-31 1993-03-31 Image memory circuit for digital processing of interlaced video signals KR940023196A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930005263A KR940023196A (en) 1993-03-31 1993-03-31 Image memory circuit for digital processing of interlaced video signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930005263A KR940023196A (en) 1993-03-31 1993-03-31 Image memory circuit for digital processing of interlaced video signals

Publications (1)

Publication Number Publication Date
KR940023196A true KR940023196A (en) 1994-10-22

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930005263A KR940023196A (en) 1993-03-31 1993-03-31 Image memory circuit for digital processing of interlaced video signals

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KR (1) KR940023196A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000044763A (en) * 1998-12-30 2000-07-15 전주범 Apparatus for converting an image signal in a plasam display panel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000044763A (en) * 1998-12-30 2000-07-15 전주범 Apparatus for converting an image signal in a plasam display panel

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