KR940022873A

KR940022873A - Thin Film Transistor Array Wiring Manufacturing Method

Info

Publication number: KR940022873A
Application number: KR1019930003119A
Authority: KR
Inventors: 김정현
Original assignee: 이헌조; 주식회사 금성사
Priority date: 1993-03-03
Filing date: 1993-03-03
Publication date: 1994-10-21

Abstract

본 발명은 박막트랜지스터의 어레이 배선제조방법에 관한 것으로 종래의 박막트랜지스터의 게이트라인(2)과 데이타라인(3)의 교차부위에서의 단락의 문제점과, 두라인사이에 존재하는 정전용량 값이 커서 게이터펄스 지연 및 누화(Crosstalk) 또는 플리커(flicker) 현상등이 발생하는 문제점이 있었다.The present invention relates to a method for manufacturing an array wiring of a thin film transistor, and a problem of a short circuit at an intersection of a gate line (2) and a data line (3) of a conventional thin film transistor, and a large capacitance value between the two lines is large. Gator pulse delay and crosstalk or flicker may occur.

따라서 본발명에서, 게이트라인(2)과 데이타라인(3) 교차부위의 차단층(7)위에 박막트랜지스터의 어레이 보호층인 절연층을 형성시켜 교차부위에서의 커패시턴스 값을 감소시킨다.Therefore, in the present invention, an insulating layer, which is an array protection layer of a thin film transistor, is formed on the blocking layer 7 at the intersection of the gate line 2 and the data line 3 to reduce the capacitance value at the intersection.

또한, 데이타라인(3) 연결금속층(10)의 배선폭을 데이타라인의 선폭보다 작게 형성할 수 있으므로, 커패시턴스 용량이 감속되어 시정수(RC time)가 줄어들어 게이트 펄스 지연이 감속됨으로써 선명한 영상을 얻을 수 있고, 두라인간의 단락의 가능성이 감소되어 수율이 향상된다.In addition, since the wiring width of the connection metal layer 10 of the data line 3 can be made smaller than the line width of the data line, the capacitance capacity is reduced, the time constant (RC time) is reduced, and the gate pulse delay is reduced, thereby obtaining a clear image. Can be reduced, the possibility of short circuit between two lines is reduced and the yield is improved.

Description

Thin Film Transistor Array Wiring Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도 본 발명의 제1실시예에 따른 박막트랜지스터의 어레이 배선 교차점을 나타낸 평면도, 제6도는 제5도의 제2실시예에 따른 공정순서도, 제7도는 제6도의 공정에서 접촉창 제조방법을 나타낸 평면도, 제8도는 제6도의 공정에서 데이타라인 제조방법을 나타낸 평면도.5 is a plan view showing an array wiring intersection point of a thin film transistor according to a first embodiment of the present invention, FIG. 6 is a process flow chart according to the second embodiment of FIG. 5, and FIG. 7 is a method of manufacturing a contact window in the process of FIG. 8 is a plan view showing a data line manufacturing method in the process shown in FIG.

Claims

Depositing and patterning a metal on the insulator 1 and forming a gate line 2 so as to be arranged in one direction with a predetermined interval, and having a predetermined interval and arranged in a direction perpendicular to the gate line 2, Forming a line 3 so as to have a discontinuity at the intersection, a process of forming a blocking layer 7 at a portion where the gate line 2 and the data line 3 cross each other, and the blocking layer ( 7) forming an insulating layer 8 on the exposed data line 3 and patterning it by a masking process to form a discontinuous data line 3 connecting contact window 9; and the contact window 9 And forming a metal layer (10) in the insulating layer (8) to connect discontinuous data lines (3).

Forming a gate line (2) on the insulator (1), forming a blocking layer (7) on the gate line (2) at the intersection with the data line, and forming the blocking layer (7) Forming a discontinuous data line 3 in a direction perpendicular to the data line 2 at a portion to be formed, and forming an insulating layer on the exposed entire surface and forming a contact line 9 for connecting the data line 3. And forming a metal layer (10) on the exposed entire surface of the data line (3) to connect the thin film transistor.

3. A method according to claim 2, wherein the blocking layer (7) is made of an insulator / semiconductor / insulator or an insulator / semiconductor layer structure.

The method of claim 2, wherein the blocking layer (7) and the data line (3) are formed so as not to contact each other when forming the data line (3).

3. The method of claim 2, wherein a contact window (9) for connecting the data lines (3) is formed above the blocking layer (7).

3. A method according to claim 2, wherein a contact window (9) for connecting the data lines (3) is formed outside the range of the blocking layer (7).

3. The method of claim 2, wherein a contact window (9) for data line connection is formed at a boundary between the blocking layer (7) and the data line (3).

The method of claim 2, wherein the wiring width of the data line (3) connection metal layer (10) is made equal to or smaller than the line width of the data line (3).

※ Note: The disclosure is based on the initial application.