KR940016844A - Nonvolatile semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same. A plurality of control electrode layers extending in the direction to which the high voltage is applied, and a predetermined region electrically insulated between the respective active regions and the respective control electrode layers and extending from the active region to a predetermined portion of the adjacent field region; 12. A nonvolatile semiconductor memory device having a plurality of floating gate electrode layers formed in the semiconductor device, wherein the device isolation structure formed in the field region includes a first field oxide layer formed between the adjacent active regions and the floating region between the adjacent floating gates. A second field oxide film formed on a first field oxide film, and the first field oxide film And a channel blocking region in the vicinity of the lower surface of the semiconductor substrate.

Accordingly, the nonvolatile semiconductor memory device of the present invention can reduce the area of the field insulating film and increase the insulating capability and the breakdown voltage by injecting channel low impurities into a portion of the field insulating film region so as not to contact the active region.

Description

Nonvolatile semiconductor memory device and manufacturing method thereof

Since this is an open matter, no full text was included.

6 to 10 are cross-sectional views showing the manufacturing method of the first embodiment of the nonvolatile semiconductor memory device according to the present invention.

Claims (16)

A plurality of active regions adjacent to each other via the field region in the semiconductor substrate and having a predetermined width and extending in a longitudinal direction, a plurality of control electrode layers extending in a direction crossing the plurality of active regions and to which a high voltage is applied; A nonvolatile semiconductor memory device having a plurality of floating gate electrode layers formed in a predetermined region electrically insulated between each active region and each control electrode layer and extending from the active region to a predetermined portion of the adjacent field region. The device isolation structure formed in the field region may include a first field oxide layer formed between the adjacent active regions, a second field oxide layer formed on the first field oxide layer between the adjacent floating gates, and the first field. And a channel blocking region in the vicinity of the surface of the semiconductor substrate under the oxide film. A nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device of claim 1, wherein the first field oxide film and the second field oxide film are sequentially formed. The nonvolatile semiconductor memory device of claim 1, wherein the total thicknesses of the first field oxide film and the second field oxide film have a thickness sufficient to prevent the field parasitic transistor from being operated by a high voltage applied to the control electrode layer. . The nonvolatile semiconductor memory device of claim 1, further comprising another channel blocking region formed of impurities having a concentration lower than that of the channel blocking region. Forming a first field oxide film on the semiconductor substrate for separating elements to be formed in an active region extending in the longitudinal direction; Forming a first conductive layer on the entire surface of the semiconductor substrate and forming a dielectric film on the first conductive layer; Forming a mask pattern having an opening in a portion where the first field oxide film is formed on the dielectric film; Etching the dielectric film exposed through the mask pattern and forming a channel blocking region near the surface of the semiconductor substrate under the first field oxide film; Oxidizing the exposed first conductive layer to form a second field oxide film on the first field oxide film; And forming a second conductive layer on the entire surface of the resultant after forming the second field oxide film. Forming a first mask pattern having an opening in a portion where a first field oxide film to be formed above the semiconductor substrate in the active region is formed; Forming a first channel blocking region in the vicinity of a surface of the semiconductor substrate through the first mask pattern; Forming a first field oxide film on said semiconductor substrate for separating elements to be formed in an active region extending in a longitudinal direction; Sequentially forming a first conductive layer and a dielectric film on the entire surface of the resultant product; Forming a second mask pattern on the dielectric film; Etching the exposed dielectric film through the second mask pattern and forming a second channel blocking region near the surface of the semiconductor substrate under the first field oxide film; Oxidizing the exposed first conductive layer to form a second field oxide film on the first field oxide film; And forming a second conductive layer on the entire surface of the resultant product. The method of claim 6, wherein an impurity concentration of the first channel blocking region is lower than that of the second channel blocking region. 7. The method of claim 6, wherein impurities are implanted by applying a lower energy to the first channel blocking region than the second channel blocking region. Forming a first field oxide film on the semiconductor substrate for separating elements to be formed in an active region extending in the longitudinal direction; Forming a first conductive layer on the entire surface of the semiconductor substrate and forming a first dielectric film on the first conductive layer; Forming a first mask pattern having an opening in a portion where the first field oxide film is formed on the first dielectric film; Etching the first dielectric film exposed through the first mask pattern and forming a first channel blocking region near the surface of the semiconductor substrate under the first field oxide film; Oxidizing the exposed first conductive layer to form a second field oxide film on the first field oxide film; Removing the first dielectric film; Forming a second conductive layer on the entire surface of the resultant product; Etching the second conductive layer by applying a second mask pattern; Forming a second dielectric film on the entire surface of the resultant product; And forming a third conductive layer on the second dielectric film. 6. The method of manufacturing a semiconductor memory device according to claim 5, wherein the silicon source is different when the first field oxide film and the second field oxide film are formed. 12. The method of claim 10, wherein the first field oxide film uses the semiconductor substrate as a silicon source, and the second field oxide film uses the first conductive layer formed on the first field oxide film as a silicon source. Method of manufacturing a semiconductor memory device. 12. The method of claim 11, wherein the first conductive layer is made of polysilicon or amorphous silicon. 6. The method of claim 5, wherein the dielectric film is formed in an ON or ONO structure. The method of claim 6, wherein the first mask pattern and the second mask pattern are the same. 10. The method of claim 9, wherein the first mask pattern and the second mask pattern are the same. 10. The method of claim 9, wherein the first dielectric film comprises a nitride film. ※ Note: The disclosure is based on the initial application.