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KR940016243A - Single In Line Memory Module (SIMM; SINGLE IN LINE MEMORY MODULE) - Google Patents

Single In Line Memory Module (SIMM; SINGLE IN LINE MEMORY MODULE) Download PDF

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Publication number
KR940016243A
KR940016243A KR1019920025630A KR920025630A KR940016243A KR 940016243 A KR940016243 A KR 940016243A KR 1019920025630 A KR1019920025630 A KR 1019920025630A KR 920025630 A KR920025630 A KR 920025630A KR 940016243 A KR940016243 A KR 940016243A
Authority
KR
South Korea
Prior art keywords
memory module
line memory
line
input
coupled
Prior art date
Application number
KR1019920025630A
Other languages
Korean (ko)
Inventor
오태엽
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019920025630A priority Critical patent/KR940016243A/en
Priority to JP5324776A priority patent/JPH077133A/en
Publication of KR940016243A publication Critical patent/KR940016243A/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Mounting Of Printed Circuit Boards And The Like (AREA)

Abstract

본 발명은 안정적인 입력 신호의 공급과 입력 잡음의 효과적인 방지가 가능한 싱글 인 라인 메모리 모듈(SIMM ; SINGLE IN LINE MEMORY MODULE)에 관하여 기술한다.The present invention describes a single in line memory module (SIMM) capable of supplying a stable input signal and effectively preventing input noise.

본 발명의 싱글 인 라인 메모리 모듈은, 인쇄 회로 기판(10)에 설치되고, 외부 접속 단자(12)와 각 메모리 소자들을 연결시키는 신호선에 결합되어 입력 고조파 잡음을 방지하기 위한 복수의 커패시터(13)를 구비한다.The single in-line memory module of the present invention is provided on a printed circuit board 10, coupled to a signal line connecting the external connection terminal 12 and the respective memory elements, a plurality of capacitors (13) for preventing input harmonic noise It is provided.

Description

싱글 인 라인 메모리 모듈(SIMM; SINGLE IN LINE MEMORY MODULE)Single In Line Memory Module (SIMM; SINGLE IN LINE MEMORY MODULE)

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도 본 발명에 의한 싱글 인 라인 메모리 모듈의 개략적인 평면도, 제 2 도는 공급 전압(VCC)과 VIL(VOLTAGE INPUT LOW LEVEL)의 관계를 나타내는 그래프.1 is a schematic plan view of a single in-line memory module according to the present invention, and FIG. 2 is a graph showing the relationship between the supply voltage VCC and the VOL (VOLTAGE INPUT LOW LEVEL).

Claims (3)

싱글 인 라인 방식의 외부 접속 단자와 복수의 메모리 소자들이 인쇄 회로 기판을 통하여 상호 접속된 싱글 인 라인 메모리 모듈에 있어서, 상기 인쇄 회로 기판(10)에 설치되고, 상기 외부 접속 단자(12)와 각 메모리 소자들을 연결시키는 신호선에 결합되어 입력 고조파 잡음을 방지하기 위한 복수의 커패시터(13)를 구비하는 것을 특징으로 하는 싱글 인 라인 메모리 모듈.In a single in-line memory module in which a single in-line external connection terminal and a plurality of memory elements are interconnected through a printed circuit board, the single in-line memory module is provided on the printed circuit board 10 and is connected to the external connection terminal 12. And a plurality of capacitors (13) coupled to a signal line connecting the memory elements to prevent input harmonic noise. 제 1 항에 있어서, 상기 입력 잡음 방지용 커패시터(13)는, 메모리 소자를 구동시키는 신호선인 RAS 및 CAS 또는 어드레스 신호선에 결합되는 것을 특징으로 하는 싱글 인 라인 메모리 모듈.2. The single in-line memory module according to claim 1, wherein the input noise preventing capacitor (13) is coupled to RAS and CAS or address signal lines which are signal lines for driving memory elements. 제 1 항에 있어서, 상기 입력 잡음 방지용 커패시터(13)는, 다른 신호선에 비하여 상대적으로 고조파의 잡음으로 인하여 약해진 입력 레벨의 신호를 가지는 입력 신호선에 결합되는 것을 특징으로 하는 싱글 인 라인 메모리 모듈.The single in-line memory module according to claim 1, wherein the input noise preventing capacitor (13) is coupled to an input signal line having a signal of an input level weakened by harmonic noise relative to other signal lines. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920025630A 1992-12-26 1992-12-26 Single In Line Memory Module (SIMM; SINGLE IN LINE MEMORY MODULE) KR940016243A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019920025630A KR940016243A (en) 1992-12-26 1992-12-26 Single In Line Memory Module (SIMM; SINGLE IN LINE MEMORY MODULE)
JP5324776A JPH077133A (en) 1992-12-26 1993-12-22 Single in-line memory module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920025630A KR940016243A (en) 1992-12-26 1992-12-26 Single In Line Memory Module (SIMM; SINGLE IN LINE MEMORY MODULE)

Publications (1)

Publication Number Publication Date
KR940016243A true KR940016243A (en) 1994-07-22

Family

ID=19346768

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920025630A KR940016243A (en) 1992-12-26 1992-12-26 Single In Line Memory Module (SIMM; SINGLE IN LINE MEMORY MODULE)

Country Status (2)

Country Link
JP (1) JPH077133A (en)
KR (1) KR940016243A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100450677B1 (en) * 2002-06-04 2004-10-01 삼성전자주식회사 Semiconductor memory device with data bus scheme for reducing high frequency noise

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7227758B2 (en) * 2003-07-21 2007-06-05 Delphi Technologies, Inc. Printed circuit board assembly with integrated connector
US7336098B2 (en) * 2004-06-30 2008-02-26 Intel Corporation High speed memory modules utilizing on-pin capacitors
US7151683B2 (en) * 2004-06-30 2006-12-19 Intel Corporation High speed memory modules utilizing on-trace capacitors
US7545651B2 (en) * 2005-04-18 2009-06-09 Hewlett-Packard Development Company, L.P. Memory module with a predetermined arrangement of pins
JP2007109337A (en) * 2005-10-14 2007-04-26 Elpida Memory Inc Semiconductor memory device and memory module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100450677B1 (en) * 2002-06-04 2004-10-01 삼성전자주식회사 Semiconductor memory device with data bus scheme for reducing high frequency noise
US7239216B2 (en) 2002-06-04 2007-07-03 Samsung Electronics Co., Ltd. Semiconductor memory device with data bus scheme for reducing high frequency noise

Also Published As

Publication number Publication date
JPH077133A (en) 1995-01-10

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Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19921226

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19921226

Comment text: Request for Examination of Application

PG1501 Laying open of application
E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 19950428

Patent event code: PE09021S01D

PC1202 Submission of document of withdrawal before decision of registration

Comment text: [Withdrawal of Procedure relating to Patent, etc.] Withdrawal (Abandonment)

Patent event code: PC12021R01D

Patent event date: 19950628

WITB Written withdrawal of application