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KR940015835A - How to Stop Address Buses in Tycom - Google Patents

How to Stop Address Buses in Tycom Download PDF

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Publication number
KR940015835A
KR940015835A KR1019920025462A KR920025462A KR940015835A KR 940015835 A KR940015835 A KR 940015835A KR 1019920025462 A KR1019920025462 A KR 1019920025462A KR 920025462 A KR920025462 A KR 920025462A KR 940015835 A KR940015835 A KR 940015835A
Authority
KR
South Korea
Prior art keywords
address
bus
abrq
tycom
group
Prior art date
Application number
KR1019920025462A
Other languages
Korean (ko)
Other versions
KR950005244B1 (en
Inventor
정기성
Original Assignee
이헌조
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이헌조, 주식회사 금성사 filed Critical 이헌조
Priority to KR1019920025462A priority Critical patent/KR950005244B1/en
Publication of KR940015835A publication Critical patent/KR940015835A/en
Application granted granted Critical
Publication of KR950005244B1 publication Critical patent/KR950005244B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/37—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

본 발명은 타이콤 시스템의 어드레스 버스 중재방법에 관한 것으로서, 종래에는 부하종류에 구별없이 페어아비 트레이션(Fair Arbitration)방식을 적용하여 일률적인 중재가 되지 못하여 시스템 효율이 저하되는 문제점이 있었다.The present invention relates to an address bus arbitration method of a Tycom system, and in the related art, a fair arbitration method is applied regardless of the load type, and thus there is a problem in that the system efficiency is lowered due to uneven arbitration.

이러한 점을 감안하여 본 발명에서는 부하의 종류별로 그룹을 분할하고 그룹별로 우선순위 가변방식(Round Robin Fashion)을 적용 함에 따라 버스 요청한 어드레스중 최우선 순위를 선별하여 상위 그룹부터 비교하고 같은 레벨의 경우 전주기에 버스를 사용한 어드레스 다음의 어드레스에 최우선 순위를 부여함으로써 공정한 버스 사용을 중재하여 시스템의 효율을 향상시킬 수 있다.In view of this, according to the present invention, the group is divided according to the types of loads, and according to the round robin fashion for each group, the highest priority among the bus requested addresses is selected and compared from the upper group. By giving priority to the address following the bus using the period, the system can be improved by arbitrating fair bus usage.

Description

타이콤 시스템의 어드레스 버스 중제방법How to Stop Address Buses in Tycom

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 버스 사용 요청 중재시 신호 흐름도, 제4도는 본 발명에 따른 중재 로직 구형 프로그램의 예시도, 제5도는 제4도에 따른 전주기의 버스 사용을 보인 상태도.FIG. 3 is a signal flow diagram of arbitration of a bus use request according to the present invention, FIG. 4 is an exemplary diagram of an arbitration logic old program according to the present invention, and FIG. 5 is a state diagram showing full cycle bus use according to FIG.

Claims (1)

선별된 임의의 어드레스(ABRQ 〈N〉가 입출력기기(IOP)에 해당하는지 판별하여 해당하면 전주기에 어드레스(ABRQ〈12)의 버스 사용여부에 따라 어드레스(ABRQ〈11ㆍㆍ12)중 하나에게 우선권을 부여하는 제1단계와, 제1단계에서 입출력기기(IOP)에 해당하지 않을때 어드레스(ABRQ〈N)가 시스템제어모듈(SCM)에 해당하면 어드레스(ABRQ〈10〉)에게 우선권을 부여하는 제2단계와, 제2단계에서 시스템제어모듈(SCM)에 해당하지 않을때 중앙처리장치(CPU)에 해당하면 전주기에 어드레스(ABRQ〈9ㆍㆍ0〉)의 버스 사용 여부에 따라 다음 어드레스에게 우선권을 부여하는 제3단계로 이루어진 것을 특징으로 하는 타이콤 시스템의 어드레스 버스 중재방법.It is determined whether the selected random address ABRQ &lt; N &gt; corresponds to the I / O device, and if so, to one of the addresses ABRQ &lt; 11 · 12 depending on whether the address ABRQ &lt; The first step of giving priority and the address ABRQ <10> is given priority when the address ABRQ <N corresponds to the system control module SCM when the first step does not correspond to the input / output device (IOP). If the CPU corresponds to the CPU when the CPU does not correspond to the system control module (SCM) in the second step, the next step depends on whether or not the bus with the address (ABRQ <9.0>) is used for the entire cycle. And a third step of giving priority to the address. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920025462A 1992-12-24 1992-12-24 Address bus intermitting method in ticom system KR950005244B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920025462A KR950005244B1 (en) 1992-12-24 1992-12-24 Address bus intermitting method in ticom system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920025462A KR950005244B1 (en) 1992-12-24 1992-12-24 Address bus intermitting method in ticom system

Publications (2)

Publication Number Publication Date
KR940015835A true KR940015835A (en) 1994-07-21
KR950005244B1 KR950005244B1 (en) 1995-05-22

Family

ID=19346638

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920025462A KR950005244B1 (en) 1992-12-24 1992-12-24 Address bus intermitting method in ticom system

Country Status (1)

Country Link
KR (1) KR950005244B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100486247B1 (en) * 2002-07-05 2005-05-03 삼성전자주식회사 Apparatus and method for controlling

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100486247B1 (en) * 2002-07-05 2005-05-03 삼성전자주식회사 Apparatus and method for controlling

Also Published As

Publication number Publication date
KR950005244B1 (en) 1995-05-22

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