KR940012659A - Bottom gate transistor manufacturing method - Google Patents
Bottom gate transistor manufacturing method Download PDFInfo
- Publication number
- KR940012659A KR940012659A KR1019920021660A KR920021660A KR940012659A KR 940012659 A KR940012659 A KR 940012659A KR 1019920021660 A KR1019920021660 A KR 1019920021660A KR 920021660 A KR920021660 A KR 920021660A KR 940012659 A KR940012659 A KR 940012659A
- Authority
- KR
- South Korea
- Prior art keywords
- gate
- bottom gate
- drain
- polycrystalline polysilicon
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract 5
- 229920005591 polysilicon Polymers 0.000 claims 4
- 239000010408 film Substances 0.000 claims 3
- 150000004767 nitrides Chemical class 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000001953 recrystallisation Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6732—Bottom-gate only TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 게이트와 드레인간의 전계를 줄여 오프(OFF)전류를 줄이는데 적당하도록 한 보텀 게이트 트랜지스터 제조방법에 관한 것으로 게이트 양 옆에 고농도의 다결정 실리콘 측벽을 형성한 후, 상기 측벽 부분을 국부산화시켜 드레인을 이 두꺼운 산화층 위에 형성시킴으로써 게이트와 드레인간의 전계를 줄여 오프(OFF) 전류를 크게 줄일 수 있을 뿐만 아니라, 게이트와 드레인간의 오프 셋(OFF SET)이 존재하지 않으므로 인해 온(ON)전류의 감소를 막을 수 있도록 한 것이다.The present invention relates to a method of manufacturing a bottom gate transistor suitable for reducing an OFF current by reducing an electric field between a gate and a drain. After forming a high concentration of polycrystalline silicon sidewalls on both sides of a gate, the sidewall portion is locally oxidized and drained. Is formed on the thick oxide layer to reduce the electric field between the gate and the drain, which greatly reduces the OFF current, and also reduces the ON current due to the absence of the OFF SET between the gate and the drain. It is to prevent it.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제3도는 본 발명에 따른 보텀 게이트 트랜지스터 제조 공정도.3 is a bottom gate transistor manufacturing process diagram according to the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920021660A KR940012659A (en) | 1992-11-18 | 1992-11-18 | Bottom gate transistor manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920021660A KR940012659A (en) | 1992-11-18 | 1992-11-18 | Bottom gate transistor manufacturing method |
Publications (1)
Publication Number | Publication Date |
---|---|
KR940012659A true KR940012659A (en) | 1994-06-24 |
Family
ID=67210994
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920021660A Ceased KR940012659A (en) | 1992-11-18 | 1992-11-18 | Bottom gate transistor manufacturing method |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR940012659A (en) |
-
1992
- 1992-11-18 KR KR1019920021660A patent/KR940012659A/en not_active Ceased
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19921118 |
|
PG1501 | Laying open of application | ||
A201 | Request for examination | ||
PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19971107 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 19921118 Comment text: Patent Application |
|
E902 | Notification of reason for refusal | ||
PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20000229 Patent event code: PE09021S01D |
|
E601 | Decision to refuse application | ||
PE0601 | Decision on rejection of patent |
Patent event date: 20000930 Comment text: Decision to Refuse Application Patent event code: PE06012S01D Patent event date: 20000229 Comment text: Notification of reason for refusal Patent event code: PE06011S01I |