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KR940012659A - Bottom gate transistor manufacturing method - Google Patents

Bottom gate transistor manufacturing method Download PDF

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Publication number
KR940012659A
KR940012659A KR1019920021660A KR920021660A KR940012659A KR 940012659 A KR940012659 A KR 940012659A KR 1019920021660 A KR1019920021660 A KR 1019920021660A KR 920021660 A KR920021660 A KR 920021660A KR 940012659 A KR940012659 A KR 940012659A
Authority
KR
South Korea
Prior art keywords
gate
bottom gate
drain
polycrystalline polysilicon
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1019920021660A
Other languages
Korean (ko)
Inventor
황명하
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019920021660A priority Critical patent/KR940012659A/en
Publication of KR940012659A publication Critical patent/KR940012659A/en
Ceased legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6729Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732Bottom-gate only TFTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6704Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 게이트와 드레인간의 전계를 줄여 오프(OFF)전류를 줄이는데 적당하도록 한 보텀 게이트 트랜지스터 제조방법에 관한 것으로 게이트 양 옆에 고농도의 다결정 실리콘 측벽을 형성한 후, 상기 측벽 부분을 국부산화시켜 드레인을 이 두꺼운 산화층 위에 형성시킴으로써 게이트와 드레인간의 전계를 줄여 오프(OFF) 전류를 크게 줄일 수 있을 뿐만 아니라, 게이트와 드레인간의 오프 셋(OFF SET)이 존재하지 않으므로 인해 온(ON)전류의 감소를 막을 수 있도록 한 것이다.The present invention relates to a method of manufacturing a bottom gate transistor suitable for reducing an OFF current by reducing an electric field between a gate and a drain. After forming a high concentration of polycrystalline silicon sidewalls on both sides of a gate, the sidewall portion is locally oxidized and drained. Is formed on the thick oxide layer to reduce the electric field between the gate and the drain, which greatly reduces the OFF current, and also reduces the ON current due to the absence of the OFF SET between the gate and the drain. It is to prevent it.

Description

보텀(Bottom) 게이트 트랜지스터 제조방법Bottom gate transistor manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 보텀 게이트 트랜지스터 제조 공정도.3 is a bottom gate transistor manufacturing process diagram according to the present invention.

Claims (1)

보텀 게이트 트랜지스터 제조 방법에 있어서, 반도체 기판에 절연층을 형성하고, 게이트 폴리 및 질화막을차례로 증착한 후 포토에치하여 게이트를 형성하는 단계와, 상기 단계후 다결정 폴리실리콘을 증착하고 이온 주입하여 고농도의 다결정 폴리실리콘을 형성한 다음 상기 다결정 폴리실리콘을 에치하여 측벽을 형성하는 단계와, 상기 단계후 측벽 부분을 국부 산화시켜 측벽위에 두꺼운 산화층을 형성하는 단계와, 상기 단계후 질화막을 제거하고, 게이트 산화막과 채널용 다결정 폴리실리콘을 차례로 증착한 다음 재결정화 공정을 실시하여 소스/드레인을 형성하는 단계를 포함하여 이루어진 보텀 게이트 박막 트랜지스터 제조방법.In the method of manufacturing a bottom gate transistor, an insulating layer is formed on a semiconductor substrate, the gate poly and nitride films are sequentially deposited and then photoetched to form a gate, and after the step, polycrystalline polysilicon is deposited and ion implanted to obtain a high concentration. Forming polycrystalline polysilicon, followed by etching the polycrystalline polysilicon to form a sidewall, and locally oxidizing the sidewall portion after the step to form a thick oxide layer on the sidewall, removing the nitride film after the step, and removing the gate A method of manufacturing a bottom gate thin film transistor comprising depositing an oxide film and polycrystalline polysilicon for a channel in sequence and then performing a recrystallization process to form a source / drain. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920021660A 1992-11-18 1992-11-18 Bottom gate transistor manufacturing method Ceased KR940012659A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920021660A KR940012659A (en) 1992-11-18 1992-11-18 Bottom gate transistor manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920021660A KR940012659A (en) 1992-11-18 1992-11-18 Bottom gate transistor manufacturing method

Publications (1)

Publication Number Publication Date
KR940012659A true KR940012659A (en) 1994-06-24

Family

ID=67210994

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920021660A Ceased KR940012659A (en) 1992-11-18 1992-11-18 Bottom gate transistor manufacturing method

Country Status (1)

Country Link
KR (1) KR940012659A (en)

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Patent event code: PA01091R01D

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Patent event date: 19921118

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