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KR940010686A - Noise reduction circuit - Google Patents

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KR940010686A
KR940010686A KR1019920020206A KR920020206A KR940010686A KR 940010686 A KR940010686 A KR 940010686A KR 1019920020206 A KR1019920020206 A KR 1019920020206A KR 920020206 A KR920020206 A KR 920020206A KR 940010686 A KR940010686 A KR 940010686A
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video signal
delayed
signal
outputting
minimum value
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KR0139782B1 (en
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황덕원
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윤종용
삼성전자 주식회사
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Priority to JP5268890A priority patent/JP2859526B2/en
Priority to CN93119833A priority patent/CN1041265C/en
Priority to DE69319840T priority patent/DE69319840T2/en
Priority to US08/143,618 priority patent/US5448309A/en
Priority to EP93308724A priority patent/EP0595663B1/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moiré or halo

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Picture Signal Circuits (AREA)

Abstract

디지탈 영상신호 처리장치에서의 영상신호의 노이즈를 제거하는 노이즈 제거회로로서, 이는 입력 영상신호(OH)를 지연하여 일 수평라인 및 이 수평라인 지연된 제1 지연 영상신호(1H)와 제2 지연 영상신호(2H)를 출력하는 지연 영상신호 출력수단과, 상기 영상신호(OH) 및 제1 지연 영상신호(1H)와, 상기 영상신호(OH) 및 상기 제2 지연 영상신호(2H)를 각각 비교하여 두값중 레벨이 작은 제1, 제2 최소값을 각각 출력하는 수평라인의 최소값 검출수단과, 상기 검출된 제1, 제2최소값들 중에서 최대값을 선택 출력하는 최대값 선택수단과, 상기 영상신호(OH) 및 제1 지연 영상신호(1H)와, 상기 영상신호(OH) 및 상기 제2 지연 영상신호(2H)를 각각 비교하여 두값중 레벨이 큰 제1, 제2최대값을 각각 출력하는 수평라인의 최대값 검출수단과, 상기 검출된 제1, 제2치대값들중에서 최소값을 선택 출력하는 최소값 선택수단과, 상기 최대값 선택수단으로 부터 출력되는 최대값과 상기 최소값 선택수단으로 부터 출력되는 최소값을 가산하여 영상신호의 수평 라인의 상관성 노이즈가 포함된 가산신호를 출력하는 가산수단과, 상기 상기 가산수단으로 부터 출력되는 가산신호에서 상기 제1 지연 영상신호를 감산하여 노이즈가 제거된 영상신호를 출력하는 감산수단으로 구성되어 있다.A noise removing circuit that removes noise of a video signal in a digital video signal processing apparatus, which delays an input video signal OH so that one horizontal line and the horizontal delayed first delayed video signal 1H and second delayed video are delayed. A delayed video signal output means for outputting a signal 2H, the video signal OH and the first delayed video signal 1H, and the video signal OH and the second delayed video signal 2H, respectively, are compared. A minimum value detecting means of a horizontal line for outputting first and second minimum values having a smaller level among the two values, a maximum value selecting means for selectively outputting a maximum value among the detected first and second minimum values, and the video signal. (OH) and the first delayed video signal (1H) and the video signal (OH) and the second delayed video signal (2H) are respectively compared to output the first and second maximum values having the higher level among the two values, respectively. A maximum value detecting means of a horizontal line and among the detected first and second band values A minimum value selecting means for selecting and outputting a minimum value, and a maximum value output from the maximum value selecting means and a minimum value output from the minimum value selecting means for outputting an addition signal including correlation noise of a horizontal line of an image signal. And subtraction means for subtracting the first delayed video signal from the addition signal outputted from the adding means and outputting a video signal from which noise is removed.

본 발명은, 영상신호의 상관성을 이용하여 영상신호에 포함된 노이즈만을 효율적으로 추출하여 제거함으로써 재생시의 해상도의 열화를 방지할 수 있다.The present invention can effectively deteriorate the resolution during reproduction by efficiently extracting and removing only the noise included in the video signal using the correlation of the video signal.

Description

노이즈 제거회로Noise reduction circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 노이즈 제거 회로도,3 is a noise removing circuit diagram according to the present invention;

제4도는 제3도의 각부분의 동작파형도.4 is an operation waveform diagram of each part of FIG.

Claims (5)

영상신호의 노이즈 제거회로에 있어서, 입력 영상신호(OH)를 지연하여 일 수평라인 및 이 수평라인 지연된 제1 지연 영상신호(1H)와 제2 지연 영상신호(2H)를 출력하는 지연 영상신호 출력수단과, 상기 영상신호(OH) 및 제1 지연 영상신호(1H)와, 상기 영상신호 (OH) 및 상기 제2 지연 영상신호 (2H)를 각각 비교하여 두값중 레벨이 작은 제1, 제2 최소값을 각각 출력하는 수평 라인의 최소값 검출수단과, 상기 검출된 제1, 제2 최소값들 중에서 최대값을 선택 출력하는 최대값 선택수단과, 상기 영상신호(OH) 및 제1 지연 영상신호(1H)와, 상기 영상신호(OH) 및 상기 제2 지연 영상신호(2H)를 각각 비교하여 두값중 레벨이 큰 제1, 제2 최대값을 각각 출력하는 수평라인의 최대값 검출수단과, 상기 검출된 제1, 제2 최대값들 중에서 최소값을 선택 출력하는 최소값 선택수단과, 상기 최대값 선택수단으로 부터 출력되는 최대값과 상기 최소값 선택수단으로 부터 출력되는 최소값을 가산하여 영상신호의 수평라인의 상관성 노이즈가 포함된 가산신호를 출력하는 가산수단과, 상기 상기 가산수단으로 부터 출력되는 가산신호에서 상기 제1 지연 영상신호를 감산하여 노이즈가 제거된 영상신호를 출력하는 감산수단으로 구성함을 특징으로 하는 회로.In the noise canceling circuit of a video signal, a delayed video signal output for delaying an input video signal OH and outputting one horizontal line and the delayed first delayed video signal 1H and the second delayed video signal 2H. Means for comparing the video signal OH and the first delayed video signal 1H with the video signal OH and the second delayed video signal 2H, respectively. Minimum value detection means of a horizontal line for outputting a minimum value, maximum value selecting means for selectively outputting a maximum value among the detected first and second minimum values, and the video signal OH and the first delayed video signal 1H. And a maximum value detecting means of a horizontal line for comparing the video signal OH and the second delayed video signal 2H, respectively, and outputting first and second maximum values having a higher level among the two values, and the detection. Minimum value selecting means for selecting and outputting a minimum value among the first and second maximum values; Addition means for outputting an addition signal including correlation noise of a horizontal line of an image signal by adding a maximum value output from said maximum value selecting means and a minimum value output from said minimum value selecting means, and from said adding means; And subtracting means for subtracting the first delayed video signal from the added signal and outputting a video signal from which noise is removed. 제1항에 있어서, 상기 수평 라인의 최소값 검출수단은, 상기 영상신호(OH)와 상기 제1 지 연 영상신호(1H)를 입력하며, 상기 입력된 영상신호들을 비교하여 두입력 중 레벨이 최소인 값을 검출하여 출력하는 제1 최소값 검출기(26)와, 상기 제1 지연 영상신호(1H)와 상기 제2 지연 영상신호(2H)를 입력하며, 상기 입력된 영상신호들을 비교하여 두입력중 레벨이 최소인 값을 검출하여 출력하는 제2 최소값 검출기(28)로 구성되어 이웃하는 수평 영상신호에 포함된 최소레벨의 노이즈를 각각 출력함을 특징으로 하는 회로.The minimum value detecting means of the horizontal line inputs the image signal OH and the first delayed image signal 1H, and compares the input image signals to minimize the level of the two inputs. A first minimum value detector 26 for detecting and outputting a value of phosphorus and a first delayed image signal 1H and a second delayed image signal 2H, and comparing the inputted image signals, And a second minimum value detector (28) for detecting and outputting a value having a minimum level, and outputting noise of a minimum level included in neighboring horizontal image signals. 제1항 또는 재2항에 있어서, 상기 수평 라인의 최대값 검출수단은, 상기 영상신호(OH)와 상기 제1 지연 영상신호(1H)를 입력하며, 상기 입력된 영상신호들을 비교하여 두입력 중 레벨이 최대인 값을 검출하여 출력하는 제1 최대값 검출기(30)와, 상기 제1 지연 영상신호(1H)와 상기 제2 지연 영상신호(2H)를 입력하며, 상기 입력된 영상신호들을 비교하여 두입력중 레벨이 최대인 값을 검출하여 출력하는 제2 최대값 검출기(32)로 구성되어 이웃하는 수평영상신호에 포함된 최대레벨의 노이즈를 각각 출력함을 특징으로 하는 회로.According to claim 1 or 2, wherein the maximum value detecting means of the horizontal line, the video signal OH and the first delayed video signal (1H) is input, comparing the input video signals and two inputs A first maximum value detector 30 which detects and outputs a value having a maximum level among the first level, a first delayed video signal 1H and a second delayed video signal 2H, and inputs the input video signals. And a second maximum detector (32) which detects and outputs a value having a maximum level between the two inputs, and outputs noise of the maximum level included in neighboring horizontal image signals. 영상신호의 노이즈 제거회로에 있어서, 영상신호(OH)을 입력하는 입력수단과, 상기 입력수단의 출력단자에 접속되어 상기 영상신호(OH)를 제1, 제2 수평라인 동안 각각 지연하여 제1 지연 영상신호(1H) 및 제2 지연 영상신호(2H)를 각각 출력하는 지연출력수단과, 상기 영상신호(OH) 및 상기 제1 지연 영상신호(1H)와, 상기 영상신호(OH) 및 제2 지연 영상신호(2H)를 각각 입력하며 상기 입력된 영상신호들을 비교하여 최소값을 각각 검출 출력하는 제1, 제2 최소값 검출기(26)(28)와, 상기 영상신호(OH) 및 상기 제1 지연 영상신호(1H)와, 상기 제1, 제2 지연 영상신호(1H)(2H)를 각각 입력하며 상기 입력된 영상신호들을 비교하여 최대값을 각각 검출 출력하는 제1, 제2 최대값 검출기(30)(32)와, 상기 제1, 제2최소값 검출기(26)(28)로 부터 각각 출력되는 최소값으로 부터 최대치를 선택 출력하는 최대값 선택기(34)와, 상기 제1, 제2 최대값 검출기(30)(32)로 부터 각각 출력되는 최대값으로부터 최소치을 선택 출력하는 최소값 선택기(36)와, 상기 최대값 선택기(34)로 부터 출력되는 최대값과 상기 최소값 선택기(36)로 부터 출력되는 최소값을 가산하여 영상신호의 수평라인의 상관성 노이즈가 포함된 가산신호를 출력하는 가산기(38)와, 상기 상기 가산기(38)로 부터 출력되는 가산신호에서 상기 제1 지연 영상신호(1H)를 감산하여 노이즈가 제거된 영상신호를 출력하는 감산기(40)로 구성함을 특징으로 하는 회로.A noise reduction circuit of a video signal, comprising: an input means for inputting a video signal OH and an output terminal of the input means, and delaying the video signal OH for a first and a second horizontal lines, respectively, for a first signal; Delay output means for outputting the delayed video signal 1H and the second delayed video signal 2H, respectively, the video signal OH and the first delayed video signal 1H, the video signal OH and the first video signal. First and second minimum value detectors 26 and 28 which respectively input two delayed image signals 2H and compare the inputted image signals to detect and output minimum values, respectively; and the image signal OH and the first First and second maximum value detectors for inputting a delayed video signal 1H and the first and second delayed video signals 1H and 2H, respectively, and comparing the input video signals to detect and output a maximum value, respectively. (30) 32 and the maximum value from the minimum value output from the first and second minimum value detectors 26 and 28, respectively. A maximum value selector 34 for selectively outputting a minimum value, a minimum value selector 36 for selectively outputting a minimum value from a maximum value respectively output from the first and second maximum value detectors 30 and 32, and the maximum value selector ( An adder 38 which adds a maximum value outputted from 34) and a minimum value outputted from the minimum value selector 36 to output an adder signal including correlation noise of a horizontal line of an image signal, and the adder 38 And a subtractor 40 for outputting a video signal from which noise is removed by subtracting the first delayed video signal 1H from the added signal output from 제4항에 있어서, 상기 지연출력수단은, 상기 입력수단으로 부터 출력되는 영상신호(OH)를 일 수평라인 지연하여된 제1 지연 영산신호(IH)를 상기 제1, 제2 최소값 검출기(26)(28)와 상기 제1, 제2 최대값 검출기(30)(32)로 공급하는 제1 지연기(22)와, 상기 제1 지연기(22)의 출력에 직렬 접속되 어 상기 지연신호(1H)를 일 수평라인 지연하여된 제2 지연 영상신호(2H)를 상기 제2 최소값 검출기(28)와 상기 제2 최대값 검출기(32)로 공급하는 제2 지연기(24)로 구성함을 특징으로 하는 회로.The first and second minimum detectors 26 of claim 4, wherein the delay output means outputs a first delayed output signal IH obtained by delaying the video signal OH output from the input means by one horizontal line. (28), a first delay unit 22 for supplying the first and second maximum value detectors 30, 32, and an output of the first delay unit 22 in series so that the delay signal And a second delayer 24 for supplying the second delayed image signal 2H obtained by delaying (1H) by one horizontal line to the second minimum value detector 28 and the second maximum value detector 32. Circuit characterized in that. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920020206A 1992-10-30 1992-10-30 Noise cancelling circuit Expired - Fee Related KR0139782B1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019920020206A KR0139782B1 (en) 1992-10-30 1992-10-30 Noise cancelling circuit
JP5268890A JP2859526B2 (en) 1992-10-30 1993-10-27 Noise reduction circuit for video signal
CN93119833A CN1041265C (en) 1992-10-30 1993-10-30 Noise canceler for video signal
DE69319840T DE69319840T2 (en) 1992-10-30 1993-11-01 Noise reduction for video signals
US08/143,618 US5448309A (en) 1992-10-30 1993-11-01 Noise canceler for video signal
EP93308724A EP0595663B1 (en) 1992-10-30 1993-11-01 Noise reduction for video signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920020206A KR0139782B1 (en) 1992-10-30 1992-10-30 Noise cancelling circuit

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KR940010686A true KR940010686A (en) 1994-05-26
KR0139782B1 KR0139782B1 (en) 1998-06-15

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KR101464134B1 (en) * 2013-05-27 2014-11-24 주식회사엘디티 Noise detection apparatus for signal inputted using serial interface and noise detection method therefor

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