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KR940010386A - Bipolar Transistors and Manufacturing Method Thereof - Google Patents

Bipolar Transistors and Manufacturing Method Thereof Download PDF

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KR940010386A
KR940010386A KR1019920020172A KR920020172A KR940010386A KR 940010386 A KR940010386 A KR 940010386A KR 1019920020172 A KR1019920020172 A KR 1019920020172A KR 920020172 A KR920020172 A KR 920020172A KR 940010386 A KR940010386 A KR 940010386A
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bipolar transistor
region
forming
manufacturing
transistor according
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KR0154764B1 (en
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윤광준
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

베이스영역상에 에미터영역이 자기정합적으로 형성되는 바이폴라 트랜지스터에서, 반도체 기판상에 형성되어있는 내부 베이스영역의 상부에 다결정 규소를 열산화시켜 산화막을 소정의 두께로 형성하고, 상기 구조의 전면에 소정의 에너지로 이온주입을 실시하면 상기 산화막이 형성되어있지 않은 내부 베이스영역의 바깥쪽 둘레에만 이온이 주입되어 고농도의 외부 베이스영역이 자기정합적으로 형성된다. 그다음 상기 산화막의 중심부를 소정두께 식각하여 개구를 형성한 후, 상기 개구의 내부 베이스영역 상부에 반대도전형의 불순물 이온은 주입하여 에미터영역을 형성하였다. 이때 상기 식각되고 남은 외륜(rim) 형상의 산화막이 스페이서가 된다.In a bipolar transistor in which an emitter region is self-aligned on a base region, an oxide film is formed to a predetermined thickness by thermally oxidizing polycrystalline silicon on top of an internal base region formed on a semiconductor substrate, and the front surface of the structure When ion implantation is performed at a predetermined energy, ions are implanted only in the outer periphery of the inner base region where the oxide film is not formed, and a high concentration of the outer base region is self-aligned. Thereafter, an opening was formed by etching a central portion of the oxide film to a predetermined thickness, and then an impurity ion of an opposite conductivity type was implanted on the inner base region of the opening to form an emitter region. In this case, the etched oxide film having the remaining outer ring becomes a spacer.

따라서 베이스전극과 연결되는 외부 베이스영역과, 에미터영역 하부의 내부 베이스영역 이 산화막으로된 스페이서에 의해 정확히 분리되어지므로 베이스영역의 길이 및 에미터와 외부 베이스영역의 간격이 자기정합적으로 균일하게 유지되므로 소자의 특성이 안정되고, 바이폴라 트랜지스터의 제조 공정이 간단하다. 또한 상기 에미터 영역 형성을 위한 이온주입 공정이나 각측 식각 공정시 상기 산화막의 일부 또는 전부가 내부 베이스 영역상에 남아있으므로 상기 반도체 기판의 표면 손상에 의한 결함이 적게 발생하므로 누설전류가 감소하여 소자의 신뢰성을 향상시킬 수 있다.Therefore, since the outer base area connected to the base electrode and the inner base area under the emitter area are exactly separated by spacers made of oxide film, the length of the base area and the distance between the emitter and the outer base area are uniformly self-aligned. As a result, the device characteristics are stabilized, and the manufacturing process of the bipolar transistor is simple. In addition, since some or all of the oxide film remains on the inner base region during the ion implantation process or the etching process for forming the emitter region, fewer defects due to surface damage of the semiconductor substrate are generated, thereby reducing leakage current. Reliability can be improved.

Description

바이폴라 트랜지스터 및 그 제조방법Bipolar Transistors and Manufacturing Method Thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 이 발명에 따른 바이폴라 트랜지스터의 단면도,2 is a cross-sectional view of a bipolar transistor according to the present invention,

제3(A)∼(E)도는 이 발명에 따른 바이폴라 트랜지스터의 제조 공정도이다.3 (A) to (E) are manufacturing process diagrams of a bipolar transistor according to the present invention.

Claims (19)

제1도전형의 반도체 기판상에 형성되어 있는 제2도전형의 매몰층과, 상기 구조의 전표면에 형성되어 있는 제2도전형의 에피층과, 상기 에피층의 일측에 상기 매몰층과 연결되도록 제2도전형의 불순물로 형싱되어 있는 콜랙터영역과, 상기 에피층의 타측에 제1도전형의 불순물로 형성되어 있는 베이스영역과, 상기 베이스영역상에 일측에 제2도전형의 불순물로 형성되어 있는 에미터영역을 구비하는 바이폴라 트랜지스티에 있어서, 상기 베이스영역이 베이스 전극과 연결되는 외부 베이스영역과 상기 에미터 영역 하부의 내부 베이스영역으로 구성되어 있으며, 상기 외부 베이스영역이 상기 내부 베이스영역에 비해 깊게 형성되어 있고, 상기 내부 및 외부 베이스영역의 경계부분상에 반도체층이 산화되어 형성된 타측의 일측이 식각되어 스페이서가 형성되어 있으며, 상기 스페이서의 타측이 상기 베이스전극에 접하고 있고, 타측은 상기 에미터영역과 연결되는 에미터전극에 전하는 것을 특징으로 하는 바이폴라 트랜지스터.The buried layer of the second conductive type formed on the semiconductor substrate of the first conductive type, the epi layer of the second conductive type formed on the entire surface of the structure, and the buried layer connected to one side of the epi layer. A collector region formed of an impurity of a second conductivity type, a base region formed of an impurity of a first conductivity type on the other side of the epi layer, and an impurity of a second conductivity type on one side of the base region. A bipolar transistor having an emitter region formed therein, wherein the base region includes an outer base region connected to a base electrode and an inner base region below the emitter region, wherein the outer base region is the inner region. It is formed deeper than the base region, and one side of the other side formed by oxidizing the semiconductor layer on the boundary portions of the inner and outer base regions is etched to form a spacer. It is, and the other side of the spacer and in contact with the base electrode, the other side of the bipolar transistor, characterized in that the charge on the emitter electrode is connected to the emitter region. 제1항에 있어서, 상기 스페이서가 다결정규소 및 비정질규소로 이루어지는 군에서 임의로 선택되는 하나의 반도체가 산회되어 형성되어 있는 바이폴라 트랜지스터.The bipolar transistor according to claim 1, wherein the spacer is formed by scattering one semiconductor arbitrarily selected from the group consisting of polycrystalline silicon and amorphous silicon. 제1항에 있어서, 상기 스페이서가 경사지도록 형성되어 있어 에미터전극량의 저촉을 원활하게 하는 바이폴라 트랜지스터.The bipolar transistor according to claim 1, wherein the spacer is formed to be inclined to smooth the touch of the emitter electrode amount. 바이폴라 트랜지스터의 제조방법에 있어서, 제1도전형의 반도체 기판상에 소자영역을 정의하기 위한 소자분리막은 형성하는 제1공정과, 상기 소자영역의 전표면에 제2도전형의 불순물로 내부 베이스영역을 형성하는 제2공정과, 상기 소자영역과 소자분리막상에 반도체층을 형성하는 제3공정과, 상기 반도체층의 상부를 소정두께 산화시켜 제1절연막을 형성하는 제4공정과, 상기 제1절연막상에 제1내산화성막을 형성하는 제4공정과, 상기 소자영역상의 제1내산화성막의 일측을 제거하여 상기 제1절연막을 노출시키는 제5공정과, 상기 노출된 제1절연막을 제거하여 상기 반도체층을 노출시키는 제6공정과, 상기 노출된 반도체층을 소정두께 제거하여 개구를 형성하는 제7공정과, 상기 구조의 전표며네 소정두께의 제2내산화성막을 형성하는 제8공정과, 상기 제2내산화성막상에 제2절연막을 형성하는 제9공정과, 상기 개구상의 제2절연막과 제2내산화성막을 순차적으로 제거하여 상기반도체층의 일측을 노출시키며 상기 개구의 둘레에 스페이서를 형성하는 제10공정과, 상기 노출된 반도체층을 산화시켜 제3절연막을 형성하는 제11공정과, 상기 내부 베이스영역의 둘레에 제2도전형의 불순물로 외부 베이스영역을 형성하는 제12공정과, 상기 제3절연막의 일측을 시작하여 에미터영역을 형성하기 위한 개구를 형성하는 제13공정과, 상기 제2및 제1내산화성막을 제거하는 제14공정과, 상기 개구하부의 내부 베이스영역 상부에 제1도전형의 불순물로 에미터영역을 형성하는 제15공정을 포함하는 바이폴라 트랜지스터의 제조방법.A method of manufacturing a bipolar transistor, comprising: a first step of forming an element isolation film for defining an element region on a semiconductor substrate of a first conductivity type; and an inner base region of an impurity of a second conductivity type on the entire surface of the element region. A second process of forming a semiconductor layer, a third process of forming a semiconductor layer on the device region and an isolation layer, a fourth process of oxidizing an upper portion of the semiconductor layer to a predetermined thickness to form a first insulating film, and the first process A fourth step of forming a first oxidation resistant film on the insulating film, a fifth step of exposing one side of the first oxidation resistant film on the device region to expose the first insulating film, and removing the exposed first insulating film A sixth step of exposing the semiconductor layer, a seventh step of removing the exposed semiconductor layer by a predetermined thickness to form an opening, and an eighth step of forming a second oxidation resistant film having a predetermined thickness of the document; Prize A ninth step of forming a second insulating film on the second oxidation resistant film, and sequentially removing the second insulating film and the second oxidation resistant film on the opening to expose one side of the semiconductor layer to form a spacer around the opening. A tenth step of forming a third insulating film by oxidizing the exposed semiconductor layer, a twelfth step of forming an outer base area with impurities of a second conductivity type around the inner base area; A thirteenth step of forming an opening for forming an emitter region starting from one side of the third insulating film, a fourteenth step of removing the second and first oxidation resistant films, and an upper portion of the inner base area under the opening A method of manufacturing a bipolar transistor, comprising a fifteenth step of forming an emitter region with an impurity of a first conductivity type. 제4항에 있어서, 상기 제1 및 제2도전형은 P 또는 N형을 서로 교차되게 임의로 선택하여 형성되는 바이폴라 트랜지스터의 제조방법.The method of claim 4, wherein the first and second conductive types are formed by arbitrarily selecting P or N types to cross each other. 제4항에 있어서, 상기 제1공정의 소자분리막이 로코스 스와미 및 스포트로 이루어지는 군에서 임의로 선택되는 하나의 소자분리 방법에 의해 형성되는 바이폴라 트랜지스터의 제조방법.The method of manufacturing a bipolar transistor according to claim 4, wherein the device isolation film of said first step is formed by one device isolation method arbitrarily selected from the group consisting of Locos swami and spot. 제4항에 있어서, 상기 제3 및 제4공정에서 반도체층 및 제1내산화성 막을 PVD 및 CVD로 이루어지는 군에서 임의로 선택되는 하나의 방법으로 형성하는 바이폴라 트랜지스터의 제조방법.The method of manufacturing a bipolar transistor according to claim 4, wherein the semiconductor layer and the first oxidation resistant film are formed by one method arbitrarily selected from the group consisting of PVD and CVD in the third and fourth processes. 제4항에 있어서, 상기 반도체층을 다결정규소 및 비정질규소로 이루어지는 군에서 임의로 선택되는 하나로 형성하는 바이폴라 트랜지스터의 제조방법.The method of manufacturing a bipolar transistor according to claim 4, wherein the semiconductor layer is formed of one selected from the group consisting of polycrystalline silicon and amorphous silicon. 제4항에 있어서, 상기 제1및 제2내산화서악은 질화규소 및 산화 알루미늄으로 이루어지는 군에서 임의로 선택되는 하나의 물질로 형성하는 바이폴라 트렌지스터의 제조방법.5. The method of claim 4, wherein the first and second oxidation resistant sacs are formed of one material arbitrarily selected from the group consisting of silicon nitride and aluminum oxide. 제4항에 있어서, 상기 개구를 형성하는 제5, 제6 및 제7공정을 습식 및 건식으로 이루어지는 군에서 임의로 선택되는 하나의 방법으로 행하는 바이폴라 트랜지스터의 제조방법.The method for manufacturing a bipolar transistor according to claim 4, wherein the fifth, sixth, and seventh steps for forming the opening are performed by one method arbitrarily selected from the group consisting of wet and dry. 제4항에 있어서, 상기 제5공정의 제2절연막을 산화규소 및 질과규소로 이루어지는 것에서 임의로 선택되는 하나의 절연물질로 형성하는 바이폴라 트랜지스터의 제조방법.The method of manufacturing a bipolar transistor according to claim 4, wherein the second insulating film of the fifth step is formed of one insulating material arbitrarily selected from silicon oxide, silicon and silicon. 제4항에 있어서, 상기 제5공정의 제2절연막을 PVD 및 CVD로 이루어지는 군에서 임의로 선택되는 하나의 방법으로 형성하는 바이폴라 트랜지스터의 제조방법.The method of manufacturing a bipolar transistor according to claim 4, wherein the second insulating film of the fifth step is formed by one method arbitrarily selected from the group consisting of PVD and CVD. 제4항에 있어서, 상기 제10공정의 식각공정을 이방성 건식식각으로 행하는 바이폴라 트랜지스터의 제조방법.The method of manufacturing a bipolar transistor according to claim 4, wherein the etching step of the tenth step is performed by anisotropic dry etching. 제4항에 있어서, 상기 제8공정의 제2내산화성막은 상기 제1내산화성막보다 얇게 형성한 후 스페이서를 형성하기 위한 제10공정시 상기 제1내산화성막이 많이 제거되지 않는 바이폴라 트랜지스터의 제조방법.5. The bipolar transistor of claim 4, wherein the second oxidation resistant film of the eighth process is thinner than the first oxidation resistant film, and the bipolar transistor is not removed much during the tenth process of forming a spacer. Way. 제4항에 있어서, 상기 제12공정의 외부베이스영역의 형성공정은 이온주입 에너지를 적당히 조절하며 주입되는 이온이 상기 제3절연막을 통과하지 못하도록 하는 바이폴라 트랜지스터의 제조방법.5. The method of claim 4, wherein the forming of the outer base region of the twelfth step adjusts ion implantation energy appropriately and prevents the implanted ions from passing through the third insulating layer. 제4항에 있어서, 상기 제13공정의 개구를 형성하는 식각 공정을 습식 및 건식으로 이루어지는 군에서 임으로 선택되는 하나의 방법으로 행하는 바이폴라 트랜지스터의 제조방법.The method of manufacturing a bipolar transistor according to claim 4, wherein the etching step of forming the opening of the thirteenth step is performed by one method selected from the group consisting of wet and dry. 제4항에 있어서, 상기 제13공정의 개구를 경사지게 형성하여 에미터 전극과의 접촉을 원활하게 하는 바이폴라 트랜지스터의 제조방법.The method of manufacturing a bipolar transistor according to claim 4, wherein the opening of the thirteenth step is formed to be inclined to facilitate contact with the emitter electrode. 제4항에 있어서, 상기 제13공정의 식각 공정시 상기 제3절연막을 소정두께 남겨두어 에미터영역을 형성하는 제15공정시 반도체 기판 표면의 손상을 방지하는 바이폴라 트랜지스터의 제조방법.The method of claim 4, wherein the semiconductor substrate is prevented from being damaged during the fifteenth step of forming an emitter region by leaving the third insulating layer a predetermined thickness during the etching process of the thirteenth step. 제4항에 있어서, 상기 제14공정의 상기 제2 및 제1내산화성막의 식각 공정을 습식 및 건식으로 이루어지는 군에서 임의로 선택되는 하나의 방법으로 행하는 바이폴라 트랜지스터의 제조방법.The method of manufacturing a bipolar transistor according to claim 4, wherein the etching of the second and first oxidation resistant films of the fourteenth step is performed by one method arbitrarily selected from the group consisting of wet and dry. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
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KR100715335B1 (en) * 2005-12-30 2007-05-08 위니아만도 주식회사 Packaged air conditioners with air cleaning
KR100753323B1 (en) * 2001-02-28 2007-08-29 쥬키 가부시키가이샤 Device for sewing

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100753323B1 (en) * 2001-02-28 2007-08-29 쥬키 가부시키가이샤 Device for sewing
KR100715335B1 (en) * 2005-12-30 2007-05-08 위니아만도 주식회사 Packaged air conditioners with air cleaning

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