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KR940010272A - Spacer Formation Method of Semiconductor Device - Google Patents

Spacer Formation Method of Semiconductor Device Download PDF

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Publication number
KR940010272A
KR940010272A KR1019920019903A KR920019903A KR940010272A KR 940010272 A KR940010272 A KR 940010272A KR 1019920019903 A KR1019920019903 A KR 1019920019903A KR 920019903 A KR920019903 A KR 920019903A KR 940010272 A KR940010272 A KR 940010272A
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KR
South Korea
Prior art keywords
spacer
insulating film
forming
gate electrode
etching
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KR1019920019903A
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Korean (ko)
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KR100248347B1 (en
Inventor
신기수
김승준
박해성
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019920019903A priority Critical patent/KR100248347B1/en
Publication of KR940010272A publication Critical patent/KR940010272A/en
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Publication of KR100248347B1 publication Critical patent/KR100248347B1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 고집적 반도체소자의 스페이서 형성방법에 관한 것으로, 소오스/드레인 영역의 외부면이 계단식 구조로 형성되어 접합리키지 패스가 발생하는 것을 방지하기 위하여, 게이트 전극 측벽에 형성되는 스페이서 하부구조가 완만한 경사를 갖도록 하는 공정기술이다.The present invention relates to a method for forming a spacer of a highly integrated semiconductor device, in which a spacer substructure formed on a sidewall of a gate electrode is smooth in order to prevent the junction rib path from occurring due to the stepped structure of the outer surface of the source / drain region. It is a process technology to have one slope.

Description

반도체소자의 스페이서 형성방법Spacer Formation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2D도는 본 발명의 제1실시예에 의해 스페이서를 2단계 식각으로 형성한후, 소오스/드레인 영역을 형성한 단면도,2A through 2D are cross-sectional views of forming a source / drain region after forming a spacer by two-step etching according to the first embodiment of the present invention;

제3A도 내지 제3F도는 본 발명의 제2실시예에 의해 스페이서를 형성하는 공정과, 소오스/드레인을 형성한 단면도.3A to 3F are cross-sectional views of forming a spacer and a source / drain according to a second embodiment of the present invention.

Claims (6)

MOSFET의 스페이서 형성방법에 있어서, 하부하부구조가 완만한 경사를 갖는 스페이서를 형성하기 위하여, 공지의 기술로 게이트 전극을 형성한 다음, 게이트 전극 상부에 스페이서용 절연막을 소정두께 형성한 다음, 스페이서용 절연막의 소정두께를 일단계 건식식각으로 식각한 다음, 스페이서용 절연막을 2단계 건식식각으로 식각하되 1단계 식각속도 보다 느린 식각속도로 식각하여 게이트 전극 측벽에 스페이서를 형성하는 것을 특징으로 하는 반도체소자의 스페이서 형성방법.In the method of forming a spacer of a MOSFET, in order to form a spacer having a gentle inclination of a lower lower structure, a gate electrode is formed by a known technique, and then an insulating film for spacers is formed on the gate electrode, and then a spacer is formed. After etching a predetermined thickness of the insulating film in one step dry etching, and then the insulating film for spacers is etched in a two-step dry etching, the semiconductor device is characterized in that the spacer is formed on the sidewall of the gate electrode by etching at an etching speed slower than the first step Spacer formation method of the. 제1항에 있어서, 상기 2단계 건식식각은 1단계 건식식각속도에 비하여 식각속도가 1/3이하로 되게 하는 것을 특징으로 하는 반도체소자의 스페이서 형성방법.The method of claim 1, wherein the two-step dry etching causes the etching speed to be 1/3 or less compared to the first-step dry etching speed. 제2항에 있어서, 상기 식각속도를 저하기시키 위하여 건식식각장비의 챔버내의 압력을 낮추어 주거나, RF파우어를 낮추어 주는 것을 특징으로 하는 반도체소자의 스페이서 형성방법.The method of claim 2, wherein the pressure in the chamber of the dry etching equipment is lowered or the RF power is lowered to lower the etching speed. MOSFET의 스페이서 형성방법에 있어서, 공지의 기술로 게이트 전극을 형성한 후, 게이트 전극 표면에 얇은 산화막을 성장시키고, 그 상부에 폴리실리콘층을 소정두께 형성하는 단계와. 폴리실리콘층 상부에 스페이서용 절연막을 소정두께 형성하고, 건식 식각공정으로 스페이서용 절연막을 식각하여 게이트 측벽에 스페이서를 형성하는 단계와, 노출된 폴리실리콘층을 건식식각공정으로 하여 하부구조가 완만하게 된 스폐이서를 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체소자의 스페이서 형성방법.A method of forming a spacer of a MOSFET, comprising: forming a gate electrode by a known technique, growing a thin oxide film on the surface of the gate electrode, and forming a polysilicon layer thereon. Forming a spacer insulating film on the polysilicon layer a predetermined thickness, etching the spacer insulating film by a dry etching process to form a spacer on the gate sidewall, and the underlying polysilicon layer is a dry etching process to smooth the underlying structure Forming a spacer in the semiconductor device. MOSFET의 스페이서 형성방법에 있어서, 공지의 기술로 게이트 전극을 형성한 후, 게이트 전극 상부에 스페이서 절연막을 이단계로 형성하되, 일단계로 식각속도가 느린 절연막을 형성하고, 이단계로 일단계보다 식각속도가 빠른 절연막을 형성하는 단계와, 상기 스페이서 절연막을 건식식각공정으로 식각하여 하부구조가 완만한 경사를 갖는 스페이서를 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체소자와 스페이서 형성방법.In the method of forming a spacer of a MOSFET, after forming a gate electrode by a known technique, a spacer insulating film is formed in two steps on the gate electrode, but in one step, an insulating film having a slow etching speed is formed, and in this step, an etching speed is higher than one step. Forming a fast insulating film, and etching the spacer insulating film by a dry etching process to form a spacer having a gentle inclination of a lower structure. 상기 제5항에 있어서, 상기 일단계로 형성되는 절연막은 HTO막으로 형성하고, 이단계로 형성되는 절연막은 TEOS막으로 형성되는 것을 특징으로 하는 반도체소자의 스페이서 형성방법.6. The method of claim 5, wherein the insulating film formed in one step is formed of an HTO film, and the insulating film formed in this step is formed of a TEOS film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920019903A 1992-10-28 1992-10-28 Spacer Formation Method of Semiconductor Device KR100248347B1 (en)

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KR1019920019903A KR100248347B1 (en) 1992-10-28 1992-10-28 Spacer Formation Method of Semiconductor Device

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KR940010272A true KR940010272A (en) 1994-05-24
KR100248347B1 KR100248347B1 (en) 2000-03-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100335483B1 (en) * 1995-11-28 2002-11-20 삼성전자 주식회사 Spacer formation method of semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100780686B1 (en) * 2001-06-29 2007-11-30 주식회사 하이닉스반도체 Manufacturing method of semiconductor device
KR100500439B1 (en) * 2002-08-14 2005-07-12 삼성전자주식회사 method for fabricating semiconductor device with gate spacer of positive slope

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* Cited by examiner, † Cited by third party
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JPH0626219B2 (en) * 1987-11-05 1994-04-06 シャープ株式会社 Ion implantation method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100335483B1 (en) * 1995-11-28 2002-11-20 삼성전자 주식회사 Spacer formation method of semiconductor device

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