KR940008715B1 - Control circuit for reflesh - Google Patents

Abstract

No content.

Description

DRAM refresh control circuit

The accompanying drawings are circuit diagrams of the present invention.

* Explanation of symbols for main parts of the drawings

10,11: Drive 20-28: Logic Gate

30-32: flip-flop 40: counter

50: dynamic tam

The present invention relates to a refresh control circuit of a DRAM (Dynamic RAM). In general, most of the popular personal computers require refreshing the DMA (Direct Memory Access) at regular intervals when the DRAM is refreshed. Refresh after generating the Wait signal. As a result of the conventional circuit for performing such a refresh operation, since the CPU is in a weighted state, there is a disadvantage in that the data processing efficiency of the CPU is reduced.

와 이를 반전 게이트(24)에 의해 반전시킨 신호가 각각 인가되고, 다른 입력단에는 사이클신호를 발생시키는 플릅플롭(31)의 출력신호가 인가된다.Accordingly, an object of the present invention is to solve the above-described drawbacks, by refreshing the CPU for T ₁ , T ₄ cycles without affecting the system operation at least 4 cycles (T ₁ -T ₄ ) required to operate the CPU. It is to provide a refresh control circuit of a DRAM that does not stay in the weight state, thereby improving the computer data processing efficiency. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The accompanying drawings are circuit diagrams of the present invention. Among the signals inputted and outputted through the CPU of the computer, addresses are transmitted to the peripheral circuits through the address bus, data is transmitted through the data bus, and control signals are transmitted through the control bus. Among the addresses A ₀ -A ₁₅ applied through the address bus, the lower 8 bit addresses A ₀ -A ₇ and the upper 9 bit addresses A ₈ -A ₁₅ are respectively passed through the line drives 10 and 11. It is applied to the address terminal of the DRAM 50, and is connected to the output terminal of the counter 40, which makes a refresh address and is applied to the address terminal of the DRAM 50 as well. The line drives 10 and 11 are enabled as output signals of the oragate 25 and 26, respectively, and an address selection signal is input to one input terminal of each oragate 25 and 26.

And a signal inverted by the inversion gate 24 are applied, respectively, and an output signal of the flop 31 for generating a cycle signal is applied to the other input terminal.

를, 열번지 기입단자에는 열번지제어신호

를, 행번지기입단자

에는 행번지제어신호

와 상기 플립플롭(31)의 반전출력단신호(ml)를 앤드게이트(28)에 의해 논리곱된 신호가 인가되고, 다른 행번지기입단자

에는 행번지제어신호

와 상기 신호(ml)를 앤드게이트(27)에 의해 논리곱된 신호가 인가된다. CPU에서 출력되는 신호로서 버스 콘트롤러(도시되어 있지 않음)에 인가되어 여러 제어신호를 출력되게 하는 제어신호

와 CPU의 동작여부를 결정해주는 제어신호

가 모두 하이레벨일때 하이신호를 플립플롭(30)의 입력단에 인가되게 앤드게이트(22,23)를 조합하고, 상기 플립플롭(30)은 반전게이트(21)를 통한 클럭(CLK)으로 동기되며, 순차연결된 플립플롭(31,32)은 클럭(CLK)으로 동기된다. 상기 플립플롭(30)은 그 출력신호를 다음의 플립플롭(31)의 압력단에 인가되고, 카운터(40)의 클리어단자에는 반전게이트(20)를 통하여 리세트신호(RESET)가 인가되며, 또한 플립플롭(31)의 반전출력단신호(ml)는 카운터(40)의 클럭 및 인에이블단자에 인가된다. 이와같은 구성을 갖는 본 발명의 DRAM 리프레쉬제어회로의 동작을 설명한다.Then, the control terminal of the DRAM 50 has a data write control signal to the data write control terminal.

The column address control terminal has a column address control signal.

, Line breaker terminal

Hang address control signal

And a signal obtained by logically multiplying the inverted output terminal signal ml of the flip-flop 31 by the AND gate 28, and another row address input terminal.

Hang address control signal

And a signal multiplied by the AND gate 27 is applied. Control signal that is output from the CPU and is applied to a bus controller (not shown) to output various control signals.

Control signal to determine whether CPU and CPU are operating

Are combined at the high level when the high signals are applied to the input terminal of the flip-flop 30, the AND gates 22 and 23 are combined, and the flip-flop 30 is synchronized with the clock CLK through the inverting gate 21. The sequentially connected flip-flops 31 and 32 are synchronized with the clock CLK. The flip-flop 30 is applied to its output signal to the pressure terminal of the next flip-flop 31, the reset signal RESET is applied to the clear terminal of the counter 40 through the inversion gate 20, The inverted output terminal signal ml of the flip-flop 31 is applied to the clock and enable terminals of the counter 40. The operation of the DRAM refresh control circuit of the present invention having such a configuration will be described.

가 모두 하이레벨상태에서 플립플롭(30)의 출력단에는 상기 클럭 T₃의 폴링엣지(Falling Edge)일때 하이신호가 출력된다. 이는 클럭 T₄의 라이징 엣지(Rising Edge)를 찾기위한 신호로 T₄의 라이징엣지에서도

는 모두 하이레벨이나 명확하게 T₄의 라이징엣지를 찾기 위해 플립플롭(30)을 사용하였다.When the reset signal RESET is initially applied, both the flip-flops 30-32 and the counter 40 are cleared. In addition, the passive state of the CPU at T ₃ -T ₄ during the clock cycle of the CPU,

Are all at the high level, the high signal is output to the output terminal of the flip-flop 30 when the falling edge of the clock T ₃ (Falling Edge). In which the rising edge of T ₄ with the signal to find the rising edge (Rising Edge) of the clock T ₄

All of them used a flip-flop (30) to find the rising edge of T _{4, which} is clearly high level.

)을 통해 일정시간 지연된 클럭을 출력하는데, 이 신호들은 서로 반전된 신호로서 클럭사이클 중 T₄의 라이징 엣지와 T₁의 라이징엣지에 있는 신호이다. 따라서, CPU의 동작에 전혀 영향을 주지않고 리프레쉬를 할수 있는 구간이다. 이때, 플립플롭(31)의 출력단(Q)신호는 오아게이트(25,26)를 통해 라이드라이브(10,11)에 인가되므로써 리프레쉬기간동안 라인 드라이브(10,11)를 하이 임피이던스 상태에 있게하여 어드레스 (A₀-A₁₅)가 DRAM(50)에 인가되지 않도록 한다. 또한, 플립플롭(31)의 반전출력단

신호는 카운터(40)를 인에이블 및 등기시켜 카운터(40)에서 계수값을 출력하여 DRAM(50)의 어드레스단자에 인가되게하고, 상기 신호의 라이징 엣지에서 카운터(4)의 내수계수값을 1증가하게 하며, 상기 신호는 또한 앤드게이트(27,28)를 통해 DRAM(50)의 행변지기 입단자에 인가되기 때문에 상기 플립플롭(31)의 반전출력단신호가 로우레벨일때 DRAM(50)을 리프레쉬시킨다. 즉, 상기 카운터(40)의 출력 어드레스를 1씩 증가하여 DRAM를 리프레쉬시킨다.In the flip-flop 31 inputting the clock of the high signal, two output terminals Q and

The clock output is delayed by a time, and these signals are inverted from each other and are signals at the rising edge of T _{4 and} the rising edge of T ₁ during the clock cycle. Therefore, the refresh can be performed without affecting the operation of the CPU at all. At this time, the output terminal Q of the flip-flop 31 is applied to the live drives 10 and 11 through the orifices 25 and 26 so that the line drives 10 and 11 are in the high impedance state during the refresh period. Ensure that addresses A ₀ -A ₁₅ are not applied to DRAM 50. In addition, the inverted output terminal of the flip-flop 31

The signal enables and registers the counter 40 to output a count value from the counter 40 so that it is applied to the address terminal of the DRAM 50, and the counter value of the counter 4 at the rising edge of the signal is 1. The signal is also applied to the row input terminal of the DRAM 50 through the AND gates 27 and 28 to refresh the DRAM 50 when the inverted output terminal signal of the flip-flop 31 is at a low level. . That is, the output address of the counter 40 is increased by one to refresh the DRAM.

와 데이터기입제어신호

및 어드레스 선택신호

는 일반적인 컴퓨터시스템에 사용되는 필수신호로서 통상의 방법으로 신호를 발생시킨다.Then, the row and column address control signals applied to the DRAM 50.

And data write control signal

And address selection signal

Is an essential signal used in a general computer system and generates a signal in a conventional manner.

As described above, the present invention has the advantage of improving the data processing efficiency of the system by refreshing the DRAM regardless of the operation of the CPU.

Claims (1)

In the memory refresh control circuit for refreshing the dynamic RAM by the CPU, the lower 8-bit address and the upper 8-bit address are connected to the DRAM 50 via the line drives 10 and 11, respectively, and the control signal of the CPU (

The output signal of the AND gate 22 to which is applied

And flip-flops 31 and 32 sequentially connected to the flip-flop 30 and logically multiplied by the AND gate 23 and connected to the flip-flop 30 and synchronized with a clock through the inversion gate 21. Is synchronously connected to the system clock, and the output terminal signal and the address selection signal of the flip-flop 31 are

The inverting gate 24 and the oragate 25 and 26 which are combined by applying the? Are connected to the output signals of the respective ora gates to disable the line drives 10 and 11 during the refresh period, and the reset signal RESET is It is connected to the reset terminal of the flip-flop (30-32) and the clear terminal of the counter 40 via the inversion gate 20, and the inverted output terminal of the flip-flop (31)

The signal is applied to the AND gates 27 and 28 at the same time as the counter 40 is enabled and synchronized to counter up, and thus the hang address control signal.

Is connected to the control terminal of the DRAM 50 so that a normal control signal of the computer system is applied to the DRAM 50 so that the clock is independent of the operation of the CPU during clock cycles T ₁ -T ₄ . A refresh control circuit for a DRAM, wherein the DRAM is refreshed during the period T ₄ , T ₁ ).

Images