KR940008328B1 - 필름 타입 반도체 패키지(F-PAC : Film-Type Package) 및 그 제조 방법 - Google Patents
필름 타입 반도체 패키지(F-PAC : Film-Type Package) 및 그 제조 방법 Download PDFInfo
- Publication number
- KR940008328B1 KR940008328B1 KR1019910017869A KR910017869A KR940008328B1 KR 940008328 B1 KR940008328 B1 KR 940008328B1 KR 1019910017869 A KR1019910017869 A KR 1019910017869A KR 910017869 A KR910017869 A KR 910017869A KR 940008328 B1 KR940008328 B1 KR 940008328B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- semiconductor package
- lead frame
- type semiconductor
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims (5)
- 본드패드(1)와 반도체칩(2), 리드프레임(5)을 절연시키는 절연테이프(6)와 리드프레임(5)의 인너리드(3)를 수축성-열경화성 수지 필름(10)으로 봉합하여서 됨을 특징으로 하는 필름 타입 반도체 패키지.
- 제1항에 있어서, 상기 수축성-열경화성 수지 필름(10)에는 반도체칩(2)과 리드프레임(5)의 접촉에 의한 굴곡으로 발생하는 공간 및 봉합불량을 방지하기 위한 범프(10a) 또는 뱅크가 형성됨을 됨을 특징으로 하는 필름 타입 반도체 패키지.
- 제1항에 있어서, 상기 수축성-열경화성 수지 필름(10)은 투명 또는 반투명인 것을 특징으로 하는 필름 타입 반도체 패키지.
- 제1항에 있어서, 상기 리드프레임(5)은 일반 P-DIP용 컨벤셔널 타입 또는 TAB용 릴타입인 것을 특징으로 하는 필름 타입 반도체 패키지.
- 반도체 패키지 제조방법에 있어서, 반도체칩(2)의 본드패드(1)와 리드프레임(5)의 인너리드(3)를 전기적으로 접속하는 본딩공정과, 수축성-열경화성 수지 필름(10)을 이송시켜 칩의 상, 하부에 위치시키는 피딩공정과, 밀착용 가열금형(20)을 이용하여 수축성-열경화성 수지 필름(10)에 열을 가하면서 칩에 밀착시키는 인캡슐레이션 공정을 포함하여 제조됨을 특징으로 하는 필름 타입 반도체 패키지의 제조방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910017869A KR940008328B1 (ko) | 1991-10-11 | 1991-10-11 | 필름 타입 반도체 패키지(F-PAC : Film-Type Package) 및 그 제조 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910017869A KR940008328B1 (ko) | 1991-10-11 | 1991-10-11 | 필름 타입 반도체 패키지(F-PAC : Film-Type Package) 및 그 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930009027A KR930009027A (ko) | 1993-05-22 |
KR940008328B1 true KR940008328B1 (ko) | 1994-09-12 |
Family
ID=19321102
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910017869A Expired - Fee Related KR940008328B1 (ko) | 1991-10-11 | 1991-10-11 | 필름 타입 반도체 패키지(F-PAC : Film-Type Package) 및 그 제조 방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR940008328B1 (ko) |
-
1991
- 1991-10-11 KR KR1019910017869A patent/KR940008328B1/ko not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR930009027A (ko) | 1993-05-22 |
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