KR940007684A - Cache memory system with small physical size tag memory - Google Patents

Abstract

The present invention relates to a cache memory system including a tag memory having a smaller physical size and a computer system including the cache memory system. The cache memory system includes a main memory 11 and a main memory 10 including a plurality of data. A cache memory 12 having one or more dataword blocks coupled to the subset of data, and used to identify which dataword block each dataword block is a copy of in main memory 10; And a cache memory 13 having an address tag associated with each dataword block, wherein the address tag includes an upper address tag and a lower address tag, wherein the upper address tag is a predetermined number of the lower numbers. It is hierarchically related to address tags.

Accordingly, the present invention can greatly reduce the physical size of the tag memory 13 while maintaining the fast average access speed of the memory system, and because of this size, it can be easily integrated on the same chip as the cache controller 14. .

Description

Cache memory system with small physical size tag memory

Since this is an open matter, no full text was included.

1 is a schematic block diagram showing a computer system of a preferred embodiment according to the present invention, FIG. 2 is a block circuit diagram showing in more detail a memory system of the computer system of FIG. 1, and FIG. 3 is a block diagram of an embodiment according to the present invention. Figure showing a tag memory storage map.

Claims (9)

A main memory including a plurality of data; A cache memory coupled to the main memory, the cache memory having one or more data word blocks as a subset of the data; an address used to identify which data word block each copy of the data word blocks is in the main memory; And a tag memory having a tag, wherein said address tag comprises an upper address tag and a lower address tag, said upper address tag being hierarchically associated with a predetermined number of said lower address tags. The memory system of claim 1, wherein the tag memory includes a valid bit having at least one bit in association with each lower address tag to indicate whether each block of the data word is valid. The memory system of claim 2, wherein the predetermined number is 2 ** n and n is an integer greater than zero. A processor; A main memory containing data used by the processor; A cache memory coupled to the processor and the may memory, the cache memory having one or more dataword blocks in a subset of the data; An address tag used to identify whether each data word block is a copy of a data word block at each specific position in the may memory includes an angular tag memory, the address tag including an upper address tag and a lower address tag, A computer upper address tag hierarchically associated with a predetermined number of said lower address tags. 5. The method of claim 4, wherein when the processor discards the block of data words, the tag address including the address from the processor is input, and the tag address from the processor and the address tag from the tag memory are input. And comparing means for inputting and comparing the address tag and the tag address to determine whether they match. 6. The apparatus of claim 5, wherein the comparing means comprises: first comparing means for comparing the upper address tag and the corresponding portion of the tag address in the address tag, and second comparing means for comparing the corresponding portion of the lower bit and the tag address Computer system comprising a. 7. The computer system of claim 6 wherein the tag memory includes a valid bit having at least one bit associated with each lower address tag to indicate whether each block of the data word is valid. 8. The computer system of claim 7, wherein the computer system further comprises cache control means for inputting a control signal from the processor and a comparison result signal from the comparison means to control the cache memory. The computer system according to claim 8, wherein the tag memory and the cache control means are configured on the same chip. ※ Note: The disclosure is based on the initial application.