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KR940006919B1 - Register shift circuit - Google Patents

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KR940006919B1
KR940006919B1 KR1019910000491A KR910000491A KR940006919B1 KR 940006919 B1 KR940006919 B1 KR 940006919B1 KR 1019910000491 A KR1019910000491 A KR 1019910000491A KR 910000491 A KR910000491 A KR 910000491A KR 940006919 B1 KR940006919 B1 KR 940006919B1
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data
shift
gnd
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KR920015380A (en
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이동훈
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금성일렉트론 주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

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Abstract

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Description

레지스터 자리이동회로Register shift circuit

제1도는 종래의 자리이동 레지스터 회로도.1 is a conventional seat shift register circuit diagram.

제2도는 본 발명에 의한 4비트 왼쪽 자리이동회로도.2 is a 4-bit left shifting circuit diagram according to the present invention.

제3도는 본 발명에 의한 4비트 오른쪽 자리이동회로도.3 is a 4-bit right shifting circuit diagram according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

ADl1∼AD30: 앤드게이트 NR11∼NR14, NR21∼NR24: 노아게이트AD l1 ~AD 30: AND gate NR 11 ~NR 14, NR 21 ~NR 24: NOR gate

I11∼I14, I21∼I24: 인버터I 11 to I 14 , I 21 to I 24 : Inverter

본 발명은 레지스터 자리이동에 관한 것으로, 특히 몇자리를 이동하더라도 동시에 자리이동을 할 필요가 있는 회로에 적당하도록 한 고속 레지스터 자리이동회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to register shifting, and more particularly, to a fast register shifting circuit suitable for a circuit that needs to shift at the same time no matter how many shifts.

제1도는 종래의 자리이동 레지스터의 회로도로서 이에 도시된 바와같이 프리세트인에이블신호(PE)와 프리세트신호(Pr0∼Pr3)가 낸드게이트(ND0∼ND3)에서 각기 낸드조합되어 플립플롭(FF0∼FF3)의 프리세트단자(Pr)에 각기 인가되고, 클럭신호(CP) 및 클리어신호(CL)가 상기 플립플롭(FF0∼FF3)의 클럭단자(CK)및 클리어단자(Cr)에 각기 공통인가되며, 직렬입력신호(SI)가 상기 플립플롭(FF3)의 세트단자(S3)에 인가됨과 아울러 인버터(II)를 통해 그의 리세트단자(R3)에 인가되며, 상기 플립플롭(FF3),(FF2)(FF1)의 출력단자

Figure kpo00001
,
Figure kpo00002
,
Figure kpo00003
가 플립플롭(FF2),(FF1),(FF0)의 세트, 리세트단자(S2,R2),(Sl,Rl),(S0,R0)에 각기 접속되어 구성된 것으로, 이 종래회로는 직병렬변환기 역할도 하는 4비트 자리이동 레지스터이다.The first turn is combined in the NAND gate, each NAND (ND 0 ~ND 3) an enable signal (PE) and the preset signal (Pr 0 ~Pr 3) preset as shown In a circuit diagram of a conventional spot shift register are respectively applied to the flip-flop preset terminals (Pr) of (FF 0 ~FF 3), the clock signal (CP) and a clear signal (CL) the clock terminal (CK) of said flip-flop (FF 0 ~FF 3) and Each of them is common to the clear terminal Cr, and a serial input signal SI is applied to the set terminal S 3 of the flip-flop FF 3 and its reset terminal R 3 through the inverter II. Is applied to the output terminals of the flip-flops (FF 3 ), (FF 2 ) (FF 1 )
Figure kpo00001
,
Figure kpo00002
,
Figure kpo00003
Is connected to a set of flip-flops (FF 2 ), (FF 1 ), (FF 0 ) and reset terminals (S 2 , R 2 ), (S l , R l ), (S 0 , R 0 ) In this configuration, this conventional circuit is a 4-bit shift register that also serves as a serial-to-parallel converter.

따라서, 직렬입력신호(SI)의 데이타가 "1011"(LSB)이라 가정하고 동작 설명을 한다. 클신호(CL)가 저전위로 인가되면, 이때 프리세트인에이브신호(PE)는 고전위이다.Therefore, the operation will be described assuming that the data of the serial input signal SI is " 1011 " (LSB). When the clock signal CL is applied at a low potential, the preset save signal PE is at a high potential.

따라서, 이때 플립플롭(FF0∼FF3)이 모두 클리어되어, 그의 출력신호(Q0,Q1,Q2,Q3)는 모두 저전위가 된다. 이후 클리어신호(CL)가 고전위로 세트되고, 프리세트인에이블신호(PE) 및 프리세트신호(Pr0∼Pr3)가 고전위로되어 낸드게이트(ND1∼ND4)에서 저전위신호가 출력된다.Therefore, at this time, the flip-flops FF 0 to FF 3 are all cleared, and the output signals Q 0 , Q 1 , Q 2 , and Q 3 are all at low potential. After that, the clear signal CL is set at high potential, the preset enable signal PE and the preset signals Pr 0 to Pr 3 are set to high potential, and a low potential signal is output from the NAND gates ND 1 to ND 4 . do.

따라서, 이때 클럭신호(CP)가 인가되면, 그 첫번째 클럭신호(CP)에 의해 플립플롭(FF3)이 클럭동작되어 직렬입력신호(SI)의 데이타 "1011"중 최하위비트 데이타인 고전위신호가 그 플립플롭(FF3)의 출력단자(Q3)로 출력된 후 플립플롭(FF2)의 세트단자(S2)에 인가되고, 이때 플립플롭(FF2∼FF0)의 출력단자(Q2∼Q0)에는 모두 저전위신호가 출력된다. 이후 두번째 클럭신호(CP)가 인가될 때 직렬입력신호(SI)의 데이타 "1011"중 2번째 비트 고전위신호가 플립플롭(FF3)의 출력단자(Q3)로 출력됨과 아울러 이전에 그 플립플롭(FF3)의 출력단자(Q3)에 출력된 고전위신호가 플립플롭(FF3)의 출력단자(Q2)로 출력되고, 이때 플립플롭(FFl),(FF0)의 출력단자(Ql),(Q0)에는 저전위신호가 출력된다. 즉, 직렬입력신호(SI)의 데이타 "1011"은 클럭신호(CP)가 인가됨에 따라 그 클럭신호(CP)에 동기를 맞춰 플립플롭(FF3∼FF0)으로 순차로 이동 출력되고, 이 과정을 표로 나타내면 하기와 같이 된다.Therefore, when the clock signal CP is applied at this time, the flip-flop FF 3 is clocked by the first clock signal CP, and the high potential signal which is the least significant bit data among the data " 1011 " the output terminal of the is applied to the set terminal (S 2) of the flip-flop output terminal (Q 3) flip-flop (FF 2) after the output of the (FF 3), wherein the flip-flop (FF 2 ~FF 0) ( Q 2 to Q 0 ) all output low potential signals. Thereafter, when the second clock signal CP is applied, the second bit high potential signal of the data "1011" of the serial input signal SI is output to the output terminal Q 3 of the flip-flop FF 3 and previously the high potential signal outputted to the output terminal (Q 3) of the flip-flop (FF 3) is output to the output terminal (Q 2) of the flip-flop (FF 3), wherein the flip-flop (FF l), (FF 0 ) The low potential signal is output to the output terminals Q l and Q 0 . That is, as the clock signal CP is applied, the data " 1011 " of the serial input signal SI is sequentially shifted and outputted as flip-flops FF 3 to FF 0 in synchronization with the clock signal CP. The process is shown in the table below.

[표 1]TABLE 1

각 클럭펄스 후의 플립플롭(FF3∼FF0)의 출력내용Output contents of flip-flop (FF 3 to FF 0 ) after each clock pulse

Figure kpo00004
Figure kpo00004

그러나, 이와같은 종래의 기술구성에 있어서는 몇자리를 이동할 것이냐에 따라 클럭이 시간축으로 이동수에 비례하여 늘어나게 되므로 많은 비트의 레지스터를 다툴 때 많은 시간을 필요로 하게 되고, 한 비트를 이동할 때 여러비트를 이동할때 걸리는 시간이 달라서 다른 회로와 응용을 할 때 타이밍적으로 어려움이 뒤따르는 단점이 있었다.However, in such a conventional technology configuration, the clock is increased in proportion to the number of movements along the time axis depending on how many digits are shifted. Therefore, a large amount of time is required when a bit of registers are to be manipulated. Due to the different time it takes to move, it has the disadvantage of timing difficulties when using other circuits and applications.

본 발명은 상기와 같은 종래의 단점을 해결하기 위하여, 클럭을 사용하지 않고 자리이동을 구현함으로써 자리이동수에 관계없이 자리이동시간을 동일하게 하고, 고속으로 자리이동을 수행할 수 있게 창안한 것으로, 이를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.In order to solve the above-mentioned disadvantages, the present invention has been made so that the seat movement time is the same regardless of the number of seat movements, and the seat movement can be performed at high speed by implementing the seat movement without using a clock. This will be described in detail with reference to the accompanying drawings.

제2도는 본 발명에 의한 4비트 왼쪽 자리이동회로도로서, 이에 도시한 바와같이 데이타(D0) 및 자리이동변수신호(C0)를 앤드게이트(ADll)를 통해 앤드조합한 후 접지신호(GND)와 노아게이트(NR11)에서 노아 조합하고, 이 신호를 인버터(I11)를 통해 왼쪽 자리이동데이타(SHL0)로 출력하며, 데이타(1),(D0) 및 자리이동변수신호(C0),(C1)를 앤드게이트(ADl2),(AD13)를 각기 통해 앤드조합한 후 노아게이트(NR12)에서 접지신호(GND)와 노아조합하고, 이 신호를 인버터(I12)를 통해 왼쪽 자리이동데이타(SHLl)로 출력하며, 데이타(D2),(Dl),(D0) 및 자리이동변수신호(C0),(C1),(C2)를 앤드게이트(ADl4),(ADl5),(AD16)를 각기 통해 앤드조합한 후 노아게이트(NR13)에서 접지신호(GND)와 노아조합하고, 이 신호를 인버터(I13)를 통해 왼쪽 자리이동데이타(SHL2)로 출력하며, 데이타(D3),(D2),(Dl),(D0) 및 자리이동변수신호(0),(Cl),(C2),(C3)를 앤드게이트(AD17),(AD18),(AD19),(AD20)를 각기 통해 앤드조합한 후 노아게이트(NRl4)에서 접지신호(GND)와 노아조합하고, 이 신호를 인버터(Il4)를 통해 왼쪽 자리이동데이타(SHL3)로 출력하게 구성한다.FIG. 2 is a four-bit left shifting circuit diagram according to the present invention. As shown in FIG. 2, the grounding signal is obtained after the AND combination of the data D 0 and the shifting shift signal C 0 through the AND gate AD ll . Noah combination is performed at GND) and Noah gate (NR 11 ), and this signal is output as left shift data (SHL 0 ) through inverter (I 11 ), and data ( 1 ), (D 0 ) and shift variable signal (C 0 ) and (C 1 ) are AND-combined through the AND gates (AD l2 ) and (AD 13 ), respectively, and then the NOA gate (NR 12 ) and the NOA are combined with the ground signal (GND). I 12 ) is output as left shift data (SHL l ), and data (D 2 ), (D l ), (D 0 ) and shift variable signal (C 0 ), (C 1 ), (C 2) ) And the end combination of the AND gates (AD l4 ), (AD l5 ), and (AD 16 ), respectively, and then the NOA gate (NR 13 ) with the ground signal (GND), and this signal is converted to the inverter (I 13 ). Exit to left shift data (SHL 2 ) via And input data (D 3 ), (D 2 ), (D l ), (D 0 ) and the displacement variable signals ( 0 ), (C l ), (C 2 ), (C 3 ) AD 17 ), (AD 18 ), (AD 19 ), and (AD 20 ) are then combined with each other, and then the NOR gate (NR l4 ) is combined with the ground signal (GND), and this signal is converted to the inverter (I l4 ). Configure to output left shift data (SHL 3 ) through.

즉, 상기 제2도의 왼쪽 자리이동회로를 논리식으로 나타내면 하기의 식과 같이 된다.That is, when the left seat shift circuit of FIG. 2 is represented by a logic equation, the following equation is obtained.

SHL0=D0. C0+GNDSHL 0 = D 0 . C 0 + GND

SHLl=Dl. C0+D0. C1+GNDSHL l = D l . C 0 + D 0 . C 1 + GND

SHL2=D2. C0+Dl. C1+D0. C2+GNDSHL 2 = D 2 . C 0 + D l . C 1 + D 0 . C 2 + GND

SHL3=D3. C0+D2. C1+Dl. C2+D0. C3＋GNDSHL 3 = D 3 . C 0 + D 2 . C 1 + D l . C 2 + D 0 . C 3 + GND

제3도는 본 발명에 의한 4비트 오른쪽 자리이동 회로로서, 이에 도시한 바와같이 데이타(D0), (Dl), (D2), (D3) 및 자리이동변수신호 (C0), (C1), (C2), (C3)를 앤드게이트(AD21), (AD22), (AD23), (AD24)를 각기 통해 애드조합한 후 노아게이트(NR21)를 통해 접지신호(GND)와 노아 조합하고, 이 신호를 인버터(I21)를 통해 오른쪽 자리동데이타(SHR0)로 출력하며, 데이타(Dl), (D2), (D3) 및 자리이동변수신호(C0), (C1), (C2)를 앤드게이트(AD25), (AD26), (AD27)를 각기 통해 앤드 조합한 후 노아게이트(NR22)를 통해 접지신호(GND)와 노아조합하고, 이 신호를 인버터(I22)를 통해 오른쪽 자리이동데이타(SHRl)로 출력하며, 데이타(D2), (D3) 및 자리이동변수신호(C0),(C1)를 앤드게이트(AD28),(AD29)를 각기 통해 앤드 조합한 후 노아게이트(NR23)를 통해 접지신호(GND)와 노아 조합하고, 이 신호를 인버터(I23)를 통해 오른쪽 자리이동데이타(SHR2)로 출력하며, 데이타(D3) 및 자리이동변수신호(C0)를 앤드게이트(AD30)를 통해 앤드조합한 후 노아게이트(NR24)를 통해 노아조합하고, 이 신호를 인버터(I24)를 통해 오른쪽 자리이동데이타(SHR3)로 출력하게 구성한다.3 is a 4-bit right shifting circuit according to the present invention, and as shown therein, the data (D 0 ), (D 1 ), (D 2 ), (D 3 ) and the shifting signal (C 0 ), (C 1 ), (C 2 ), and (C 3 ) are adjoined through AND gates (AD 21 ), (AD 22 ), (AD 23 ), and (AD 24 ), respectively, and then noah gate (NR 21 ) Noah combination with the ground signal (GND) through, and outputs this signal to the right digit data (SHR 0 ) through the inverter (I 21 ), data (D l ), (D 2 ), (D 3 ) and digits After moving and combining the moving variable signals (C 0 ), (C 1 ), and (C 2 ) through the AND gates (AD 25 ), (AD 26 ), and (AD 27 ), respectively, ground through the NOA gate (NR 22 ). Noah combination with the signal (GND), and outputs this signal as the right shifting data (SHR l ) through the inverter (I 22 ), the data (D 2 ), (D 3 ) and the shifting variable signal (C 0 ) , the AND gate (C 1) (AD 28) , the ground signal through the NOR gate (NR 23) and then combined with each of the end (AD 29) ( GND) and Noah are combined, and this signal is output through the inverter I 23 to the right shift data (SHR 2 ), and the data (D 3 ) and the shift signal (C 0 ) are converted into the AND gate (AD 30 ). After combining the AND through the Noah gate (NR 24 ) and Noa combination, and configured to output the signal to the right seat shift data (SHR 3 ) through the inverter (I 24 ).

즉, 상기 오른쪽 자리이동회로를 논리식으로 나타내면 하기의 식과 같이 된다.In other words, the right seat shift circuit is represented by the following equation.

SHL3=GND+D3. C0 SHL 3 = GND + D 3 . C 0

SHL2=GND+D3. C1+D2. C0 SHL 2 = GND + D 3 . C 1 + D 2 . C 0

SHL1=GND＋D3. C2＋D2. C1+D1. C0 SHL 1 = GND + D 3 . C 2 + D 2 . C 1 + D 1 . C 0

SHL0=GND+D3. C3＋D2.C2+Dl. Cl+D0. C0 SHL 0 = GND + D 3 . C 3 + D 2. C 2 + D l . C l + D 0 . C 0

상기에서 데이타(D0∼D3), 자리이동변수신호(C0∼C3), 왼쪽 자리이동데이타(SHL0∼SHL3)및 오른쪽 자리이동데이타(SHR0∼SHR3)의 각 첨자인 숫자는 비트수를 나타낸다.The subscripts of the data (D 0 to D 3 ), the shift variable signal (C 0 to C 3 ), the left shift data (SHL 0 to SHL 3 ), and the right shift data (SHR 0 to SHR 3 ) The number represents the number of bits.

그리고, 상기에서는 4비트 자리이동회로를 예로 들었으나, 그 논리식에 따라 n비트 자리이동회로로 구현할 수 있다.In the above description, the 4-bit shifting circuit is taken as an example. However, the 4-bit shifting circuit may be implemented as an n-bit shifting circuit.

이와같이 구성된 본 발명의 작용효과를 자리이동될 레지스터의 입력데이타(Dn)가 4비트의 데이타(D0∼D3)이고, 몇자리를 이동할 것인가를 정해주는 자리이동변수(Cn)가 4비트의 자리이동변수신호(C0∼C3)일 경우를 예로들어 설명한다.According to the effect of the present invention configured as described above, the input data Dn of the register to be shifted is 4 bits of data D 0 to D 3 , and the shifting variable Cn which determines how many shifts is shifted is 4 bits. The case of the digit shift variable signals C 0 to C 3 will be described as an example.

우선, 제2도의 왼쪽 자리이동회로에서 0비트 왼쪽 자리이동인 경우에는 자리이동변수신호(C0∼C3)가 C0=1, C1-C2=C3=0로 입려되고, 이에 따라, 데이타(D0∼D3)는 하기와 같이 왼쪽 자리이동데이타(SHL0∼SHL3)로 출력된다.First, in the case of 0-bit left-digit shift in the left-digit shift circuit of FIG. 2, the shift parameter signals C 0 to C 3 are applied as C 0 = 1 and C 1 -C 2 = C 3 = 0. Accordingly, data (D 0 ~D 3) is output to the left shifts data (SHL 0 ~SHL 3) as follows.

SHL0=D0, SHL1=Dl, SHL2=D2, SHL3=D3 SHL 0 = D 0 , SHL 1 = D l , SHL 2 = D 2 , SHL 3 = D 3

또한, 1비트 왼쪽 자리이동인 경우에는 자리이동변수신호(C0∼C3)가 C1=1, C0-C2=C3=0와 같이 입력되고, 이에 따라 데이타(D0∼D3)는 좌측으로 1비트 이동된 곁과로 되어 왼쪽 자리이동데이타(SHL0∼SHL3)가 하기와 같이 출력된다.Further, when the 1-bit left shifts, the shifts variable signal (C 0 ~C 3) is input as C 1 = 1, C 0 -C 2 = C 3 = 0, thus the data (D 0 ~D 3 ) is the side shifted 1 bit to the left, and the left shift data SHL 0 to SHL 3 is output as follows.

SHL0=0, SHL1=D0, SHL2=Dl, SHL3=D2 SHL 0 = 0, SHL 1 = D 0 , SHL 2 = D l , SHL 3 = D 2

또한, 2비트 왼쪽 자리이동인 경우에는 C2=1, C0=C1=C3=0로 되어, SHL0=0, SHLl=0, SHL2=D0, SHL3=D1로 되고, 3비트 왼쪽 자리이동인 경우에는 C3=1, C0=C1=C2=0로 되어, SHL0=0, SHL1=0,SHL2=0, SHL3=D0이 된다.In the case of 2-bit left shift, C 2 = 1, C 0 = C 1 = C 3 = 0 , and SHL 0 = 0, SHL l = 0, SHL 2 = D 0 , SHL 3 = D 1 In case of 3-bit left shift, C 3 = 1, C 0 = C 1 = C 2 = 0, SHL 0 = 0, SHL 1 = 0, SHL 2 = 0, SHL 3 = D 0 .

또한, 제3도의 오른쪽 자리이동회로도 상기에서 설명한 왼쪽 자리이동회로와 동일원리로 이동된다. 즉, 자리이동될 레지스터의 입력데이타(D0∼D3)는 자리이동변수신호(C0∼C3)에 따라 그에 해당하는 비트만큼 오른쪽으로 이동되고 오른쪽 자리이동데이타(SHR0∼SHR3)로 출력된다.Also, the right seat shift circuit of FIG. 3 is also moved in the same principle as the left seat shift circuit described above. That is, the input data (D 0 to D 3 ) of the register to be shifted is shifted to the right by the corresponding bit according to the shift variable signal (C 0 to C 3 ) and the right shifting data (SHR 0 to SHR 3 ) Is output.

이상에서 설명한 바와같이 본 발명에 따른 레지스터 자리이동회로는 레지스터 값을 자리이동함에 있어서 클럭을 사용하지 않고 자리이동을 구현함으로써 자리이동 수에 관계없이 자리이동하는 시간이 동일하고, 또한 단순한 논리소자의 지연만 발생함으로써 고속 자리이동을 수행할 수 있는 효과가 있게 된다.As described above, the register shifting circuit according to the present invention implements shifting without using a clock in shifting a register value, and thus the shifting time is the same regardless of the number of shifts, and a simple logic element Since only a delay occurs, there is an effect of performing fast shifting.

Claims (1)

자리이동할 레지스터의 입력데이타(D0∼Dn), 자리이동변수신호(C0∼Cn) 및 접지신호(GND)를 입력받아, 왼쪽 자리이동데이타(SHL0∼SHLn) 및 오른쪽 자리이동데이타(SHR0∼SHRn)를 논리식 SHLk=Dk. C0+Dk-l. C1+…+D0. Ck+GND 및 SHRk=GND+C0·Dk+C1·Dk+1+…+Ck·Dk+k(단, K는 비트번호임)으로 각기 논리조합하여 출력하게 구성된 것을 특징으로 하는 레지스터 자리이동회로.Receive the input data (D 0 ~ Dn), the shift variable signal (C 0 ~ Cn) and the ground signal (GND) of the register to be shifted, and the left shift data (SHL 0 to SHLn) and the right shift data (SHR). 0 to SHRn) using the logical formula SHL k = D k . C 0 + D kl . C 1 +... + D 0 . C k + GND and SHR k = GND + C 0 D k + C 1 D k + 1 +. + C k · D k + k (where K is a bit number), the register digit shift circuit, characterized in that configured to output each logical combination.
KR1019910000491A 1991-01-15 1991-01-15 Register shift circuit Expired - Fee Related KR940006919B1 (en)

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KR1019910000491A KR940006919B1 (en) 1991-01-15 1991-01-15 Register shift circuit

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Application Number Priority Date Filing Date Title
KR1019910000491A KR940006919B1 (en) 1991-01-15 1991-01-15 Register shift circuit

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KR940006919B1 true KR940006919B1 (en) 1994-07-29

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