KR940006602Y1 - Circuit for controlling power of electronic circuit - Google Patents
Circuit for controlling power of electronic circuit Download PDFInfo
- Publication number
- KR940006602Y1 KR940006602Y1 KR2019890005410U KR890005410U KR940006602Y1 KR 940006602 Y1 KR940006602 Y1 KR 940006602Y1 KR 2019890005410 U KR2019890005410 U KR 2019890005410U KR 890005410 U KR890005410 U KR 890005410U KR 940006602 Y1 KR940006602 Y1 KR 940006602Y1
- Authority
- KR
- South Korea
- Prior art keywords
- output
- inverter
- exclusive
- circuit
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000003990 capacitor Substances 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
내용 없음.No content.
Description
제1도는 본고안에 따른 전자회로의 파워 제어회로도.1 is a power control circuit diagram of an electronic circuit according to the present invention.
제2도는 본고안 회로에 따른 각부 파형도.2 is a waveform diagram of each part according to the present circuit.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
N1~N4: 인버터 D1: 다이오드N 1 to N 4 : Inverter D 1 : Diode
R1~R8: 저항 C1: 콘덴서R 1 to R 8 : Resistor C 1 : Capacitor
G1,G2: 익스크루시브 노아게이트 U1: D래치G 1 , G 2 : Exclusive Noah gate U 1 : D latch
본고안은 전자회로에서 전원 공급이후 대기 상태에서의 불필요한 전력소모를 제거하고 동작상태에서만 인가전압원을 공급하는 파워(Power)제어회로에 관한 것이다.The present invention relates to a power control circuit that removes unnecessary power consumption in the standby state after power supply from an electronic circuit and supplies an applied voltage source only in an operating state.
일반적으로 휴대용 전자계산기등에서 건전지의 수명을 연장하기 위하여 입력이 들어오지 않는 상태에서 일정시간이 경과되면 자동적으로 전원이 차단되도록 하는 경우가 있으나 대기상태에서 불필요한 전력을 소모하게 되는 결점이 있다.In general, in order to extend the life of the battery in a portable electronic calculator, there is a case that the power is automatically cut off after a certain period of time in the state of no input, but consumes unnecessary power in the standby state.
본고안은 이와같은 종래의 결점을 해결하기위한 것으로 이하에서 첨부도면을 참조하여 본고안의 구성 및 동작을 설명하면 다음과 같다.The present invention is to solve the above-mentioned drawbacks. Hereinafter, the construction and operation of the present invention will be described with reference to the accompanying drawings.
먼저 제1도에서 그 구성을 보면, 입력신호단(가)는 인버터(N1)와 익스크루시브 노아게이트(G2)의 한측입력으로 동시 연결됨과 동시에 저항(R3)을 거쳐 접지되고 인버터(N1)의 출력은 다이오드(D1)의 캐소우드와 연결되고 다이오드(D1)의 애노우드는 (나) 저항(R1)을 거쳐 전원(VDD)과 연결되고 콘덴서(C1)를 거쳐서는 접지됨과 동시에 저항(R2)을 거쳐 인버터(N2)의 입력단과 인버터(N4)을 출력단에 공통 연결되고 인버터(N2)의 출력은 인버터(N3,N4)의 입력으로 동시 연결되고, 인버터(N3)의 출력(다)는 익스크루시브 노아게이트(G2)의 나머지 한측 입력으로 연결되고 익스크루시브 노아게이트(G2)의 출력은 익스크루시브 노아게이트(G1)의 한측 입력으로 연결됨과 동시에 D래치(U1)의 클락단(CK)으로 연결되고 D래치(U1)의 Q출력은 익스크루시브 노아게이트(G1)의 나머지 한측 입력으로 연결되는 동시에 출력(OUT)이 되고, 익스크루시브 노아게이트(G1)의 출력은 D래치(U1)의 D단으로 연결되는 구성이다.First, the configuration of FIG. 1 shows that the input signal terminal A is simultaneously connected to one input of the inverter N 1 and the exclusive noah gate G 2 , and is grounded through the resistor R 3 and simultaneously connected to the inverter. (N 1), the output is a diode (D 1) in connection with her know-lifting (B), the resistance (R 1) a power supply (VDD) through the connection with the cathode and a diode (D 1) and capacitor (C 1) of It is grounded at the same time, and the input terminal of the inverter N 2 and the inverter N 4 are commonly connected to the output terminal through the resistor R 2 , and the output of the inverter N 2 is input to the inverters N 3 and N 4 . the output of being simultaneously connected to the inverter (N 3) (c) is exclusive NOR gate (G 2), the remaining one side connected to the input and the exclusive output of the NOR gate (G 2) is exclusive NOR gate (G in 1) connected to the clock stage (CK) at the same time and fixed to one side input D latch (U 1) and the Q output of the D latch (U 1) of the Exclusive Agate at the same time being connected to the remaining one side of the input (G 1) and the output (OUT), the output of the exclusive NOR gate (G 1) is configured to be connected to the D terminal of the D latch (U 1).
상기 구성회로의 동작상태를 설명하면, 필요한 입력이 인가되기 전에는 입력단(가)은 "로우"상태를 유지한다.Referring to the operating state of the configuration circuit, the input stage keeps the "low" state until the required input is applied.
그러므로 인버터(N1)출력은 "하이"가되어 다이오드(D1)이 역방향으로 되고, 이때 전원(VDD)이 저항(R1)에 의해 전압 강하되어 콘덴서(C1)에 충전되므로 "나"점 전압은 "하이"로된다.Therefore, the inverter N 1 output becomes "high" so that the diode D 1 is reversed. At this time, the power supply VDD is voltage-dropped by the resistor R 1 and charged to the capacitor C 1 . The point voltage becomes "high".
"나"점전압이 "하이"이면 인버터(N2,N3)를 거친 출력 "다"는 "하이"로 되므로 익스크루시브 노아게이트(G2)의 출력은 "로우"가되어 래치(U1)의 클락단(CK)으로 인가된다. 이때 익스크루시브 노아게이트(G1)에의한 D래치(U1)의 D입력은 "하이"상태이고, 출력 Q는 로우상태로 된다.When the "I" point voltage is "high", the output "high" through the inverters N 2 and N 3 becomes "high", so the output of the exclusive noah gate G 2 is "low" and the latch U 1 ) is applied to the clock stage CK. At this time, the D input of the D latch U 1 by the exclusive noar gate G 1 is in the "high" state, and the output Q is in the low state.
입력단(가)이 "하이"상태로 되면 인버터(N1)를 거친 출력이 "로우"로 되므로 다이오드(D1)는 정방향이 되어 전원(VDD)이 다이오드(D1)를 통해 흐르므로 콘덴서(C1)에 충전된 전압이 저항(R3)과 콘덴서(C1)시 정수에 비례하여 방전하게 되어 시간 지연을 갖게된다.When the input terminal is in the "high" state, the output through the inverter N 1 becomes "low", so the diode D 1 is in the forward direction and the power supply VDD flows through the diode D 1 . the voltage charged in the C 1) is discharged in proportion to the resistance (R 3) and capacitor (C 1) time constant will have a time delay.
따라서, "나"점전압은 제2도 "나"파형과 같게되고, 콘덴서(C1)가 방전하는 동안 인버터(N2,N3)를 거친 신호는 제2도 "다"와같이 "하이"가 되므로 인버터(N3)출력(하이)과 입력(하이)신호를 익스크루시브 노아게이트(G2)에 의해 논리화되어 (제2도CK파형) D래치(U1)의 클락(CK)에는 "하이"신호가 인가된다.Thus, the "I" point voltage becomes equal to the second degree "I" waveform, and the signal passing through the inverters N 2 and N 3 while the capacitor C 1 discharges is "high" as shown in the second degree "C". Inverter (N 3 ) output (high) and input (high) signals are logicalized by an Exclusive Noah gate (G 2 ) (Fig. 2 CK waveform) and the clock (CK of D latch (U 1 ) ), A "high" signal is applied.
그리고, D래치(U1)의 D로 입력하는 익스크루시브 노아게이트(G1)의 출력은 "하이"상태를 유지하다가 (콘덴서(C1)가 방전하는 동안) 인버터 풀력(다)이 "로우"로 떨어지게 되면 익스크루시브 노아게이트(G2)의 출력이 "로우"로되므로 "로우"상태로 변하게 된다.In addition, the output of the exclusive no-gate G 1 , which is input to D of the D latch U 1 , remains “high”, and the inverter pull power (d) is “high” while the capacitor C 1 discharges. When it falls to "low", the output of the exclusive noah gate (G 2 ) is "low", thereby changing to a "low" state.
이것은 이후 D래치(U1)의 클락단(CK)에 입력이 들어옴에 따라 출력Q에 영향을 미치게된다.This then affects the output Q as the input enters the clock stage CK of D latch U 1 .
결국 입력이 들어오는 기간동안에는 D래치(U1)의 Q출력이 "하이"상태가 되고, 대기 상태에서는 "로우"상태로 되기 때문에 (제2도 Q파형) 이것을 전자회로의 인가전원으로 사용하면 대기상태에서는 본고안의 파워 제어회로에만 전원을 인가하면 되기 때문에 전력소모를 극소화한다.As a result, the Q output of the D latch (U 1 ) becomes "high" during the input period, and becomes "low" in the standby state (Figure 2 Q waveform). In this state, power is applied only to the power control circuit in this paper, thereby minimizing power consumption.
따라서 본고안은 필요시에만 전력을 소모하므로 건전지등을 사용한 제품에서 건전지의 수명을 연장시킬 수 있고, 안전작업을 요하는 동작을 구동시키는 전자회로에서는 제어회로 입력부의 조건을 규정하여 위험 발생시 동작을 멈추는 등 여러 분야에서 사용할 수 있는 효과가 있다.Therefore, this paper consumes power only when it is necessary, so it can extend the life of battery in products using batteries, etc., and in electronic circuits that drive the operation that requires safety work, it regulates the condition of control circuit input part to operate in case of danger. It can be used in various fields such as stopping.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019890005410U KR940006602Y1 (en) | 1989-04-28 | 1989-04-28 | Circuit for controlling power of electronic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019890005410U KR940006602Y1 (en) | 1989-04-28 | 1989-04-28 | Circuit for controlling power of electronic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR900019430U KR900019430U (en) | 1990-11-09 |
| KR940006602Y1 true KR940006602Y1 (en) | 1994-09-26 |
Family
ID=19285594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019890005410U Expired - Lifetime KR940006602Y1 (en) | 1989-04-28 | 1989-04-28 | Circuit for controlling power of electronic circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR940006602Y1 (en) |
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1989
- 1989-04-28 KR KR2019890005410U patent/KR940006602Y1/en not_active Expired - Lifetime
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| Publication number | Publication date |
|---|---|
| KR900019430U (en) | 1990-11-09 |
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| UA0108 | Application for utility model registration |
Comment text: Application for Utility Model Registration Patent event code: UA01011R08D Patent event date: 19890428 |
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| UG1501 | Laying open of application | ||
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Patent event date: 19920312 Patent event code: UA02012R01D Comment text: Request for Examination of Application Patent event date: 19890428 Patent event code: UA02011R01I Comment text: Application for Utility Model Registration |
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| UG1604 | Publication of application |
Patent event code: UG16041S01I Comment text: Decision on Publication of Application Patent event date: 19940831 |
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| E701 | Decision to grant or registration of patent right | ||
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