KR940006084B1 - VSMP (VERTICAL SMALL MOUNTING PACKAGE) Structure and Manufacturing Method - Google Patents

Abstract

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Description

VSMP (VERTICAL SMALL MOUNTING PACKAGE) Structure and Manufacturing Method

1 to 3 are diagrams showing the configuration of a conventional single in line package (SIP).

2 is a plan view of the inside of FIG.

3 is a view showing a state in which a conventional Sip on the PCB.

4 to 7 are views for explaining a vertical small mounting package (VSMP) according to the present invention, Figures 4 and 5 are cross-sectional views showing the configuration of the VSMP according to the present invention.

6 is an internal plan view of FIG. 4 showing the internal structure of the VSMP according to the present invention in detail.

7 is a view showing a state in which the VSMP of the present invention on the PCB.

* Explanation of symbols for main parts of the drawings

11 semiconductor chip 11a bond pad

12, 12a, 12b: inner lead and long, shortened inner lead 13: lead frame

14: insulating tape 15: metal wire

16: molding compound 16a: molding line

17: outlead 18: outlead insertion groove

19: support bar 20: substrate (PCB)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package structure having a surface-mounted vertical shape and a fabrication method thereof, and in particular, to VMSMP suitable for a module package (VSMP: VERTICAL SMALL MOUNTING PACKAGE or less, "VSMP It refers to a structure and a manufacturing method thereof. Generally, a multi chip module (hereinafter, referred to as "MCM") configured to perform a function required by mounting several packages each having various functions on a single board (PCB). Single in-line package (hereinafter, abbreviated as " SIP ") is a plurality of bond pads 1a having external connection terminals at both sides as shown in FIG. 1 and FIG. Is provided with a semiconductor chip 1, a paddle 2 to which the semiconductor chip 1 is attached, a lead frame 4 having a plurality of leads 3, and an inner lead 3a of the lead frame 4. ) And a plurality of metal wires 5 electrically connecting and connecting the bond pads 1a of the semiconductor chip 1, and the semiconductor chip 1 and the lead frame 4 include an out lead 3b. It consists of an epoxy molding compound (EMC) (6) for molding a portion, the conventional SIP is configured as As shown in FIG. 3, the plurality of outleads 3b protruding out of the package are inserted into the lead insertion holes 7a of the substrate 7 to be fixed by soldering on the back surface thereof. By using a pin through hole (PTH) method, several SIPs are mounted on the substrate 7 to expand the memory capacity or to perform various desired functions.

Looking at the conventional manufacturing method of such SIP, first, a die attach for attaching the semiconductor chip 1 separately separated by a sawing process onto the paddle 2 of the lead frame 4 using insulating tape. Performing a die attach process, and electrically connecting and bonding the bond pad 1a of the die-attached chip 1 and the inner lead 3a of the lead frame 4 using the metal wires 5. The wire bonding process is performed, and in this way, a molding process of sealing the chip in which the wire bonding process is completed with the epoxy molding compound 6 is performed and cured, and then the lead of the molded package is cut and bent into an appropriate shape. A trimming / forming process to be formed is performed and fabricated in the order of a conventional plating process and a deflash process.

In addition, in recent years, although the lead is manufactured in the form of a lead on chip (STZIP) of a lead on chip (Lead on chip) type, the shape of the outlead is not significantly changed.

In the conventional SIP manufactured as described above, the plurality of outleads 3b protruding out of the package are inserted into the lead insertion holes 7a of the substrate 7, and then soldered on the back surface thereof to be mounted on the substrate 7. It is supposed to be.

However, the conventional SIP as described above has a lot of manufacturing process of the package, the manufacturing cost is high, the package shield (PKG Yield) is lowered by the handling or mechanical impact during the package manufacturing, the paddle (2) size of the lead frame (4) relative to the package area Due to the large size, there was a defect that caused a package crack during solder reflow due to a difference in coefficient of thermal expansion.

In addition, since the lead insertion type when the package is mounted, a connection failure may occur due to a poor insertion of the lead insertion hole 7a due to the deformation of the lead 3, and the mounting height is increased because the outlead 3b protrudes to the outside, thereby increasing the chip in the package. (1) Since the margin of the paddle 2 is required at the time of internalization, the package has a defect that becomes large.

In view of this, an object of the present invention is to reduce the number of manufacturing steps of the package and to surface mount the package, and to minimize the margin of the paddle in the package, thereby increasing the reliability of the package and reducing the size of the package. The present invention provides a package structure and a manufacturing method thereof.

An object of the present invention as described above is a memory chip having a plurality of bond pads, which are external connection terminals at both sides, an inner lead connected to the bond pad and metal wire of the chip, and a lead frame having a short COL shape; And an insulating tape for attaching the chip to the lead frame, and an epoxy molding compound for sealing the chip, and forming an outlead insertion groove on one side of the epoxy molding compound to protrude outwardly. It is achieved by providing a VSMP structure and a method of manufacturing the same, characterized in that it is configured to be surface mounted on a substrate by bending insertion.

The VSMP according to the present invention configured as described above can reduce manufacturing costs since the process after tripping / forming is omitted, and can be prevented from contact failure due to lead deformation because the surface is mounted on the substrate, and the thermal expansion coefficient difference because the paddle of the lead frame is removed. Due to this, it is possible to reduce the package crack phenomenon and increase the occupied area of the chip compared to the package, so that it can be applied to a large memory chip.

Hereinafter, a preferred embodiment of the accompanying drawings of the present invention will be described in more detail.

As shown in FIGS. 4 to 6, the VSMP according to the present invention includes a semiconductor chip 11 having a plurality of bond pads 11a which are external connection terminals at both sides thereof, and an outside of the semiconductor chip 11. A lead frame 13 made of a long, short chip-on-lead (COL) type having an inner lead 12 connected to a connection terminal, and for fixing and fixing the semiconductor chip 11 to the lead frame 13. The wire bonding and the plurality of metal wires 15 for electrically connecting the insulating techi 14, the bond pad 11a of the semiconductor chip 11, and the inner lead 12 of the lead frame 13 are completed. The lead frame 13 is provided with an epoxy molding compound 16 that seals to protect the chip 11, and protrudes outwardly on one side of the molding line 16a molded by the epoxy molding compound 16. An outlead insertion groove 18 into which the outlead 17 is bent and inserted may be formed to surface mount the substrate. In the drawing is configured to lock, reference numeral 19 is shown supported by a bar.

The inner lead 12 of the lead frame 13 is arranged in sequence with the short lead 12a and the long lead 12b, and ends of the leads 12a and 12b are connected to the substrate. The outlead 17 is extended by a predetermined length and is supported by the support bar 19 formed at the other end.

The inner lead 12 of the lead frame 13 configured as described above is electrically connected by the bond pad 11a and the metal wire 15 of the semiconductor chip 11 mounted thereon, as shown in FIG. As described above, wire bonding may be performed at both sides, and wire bonding may be performed at one side although not shown, but wire bonding may be performed at both sides due to the characteristics of the package.

In addition, a chip seating portion for facilitating the mounting of the chip 11 is formed in the inner lead 12 portion of the lead frame 13 on which the semiconductor chip 11 is mounted. They are formed by bending them downward at a predetermined angle.

On the other hand, the outlead insertion groove 18 formed on one side of the molding line 16a is a groove for bending inserting the outlead 17 protruding outward and exposed to the surface without protruding the outlead 17 to the outside. By mounting the surface on the substrate 20 as shown in FIG. 7, the mounting height can be reduced.

In addition, the outlead insertion groove 18 may be formed in a plurality of independent respective corresponding to each of the leads 17 on one side of the molding line 16a, or may form an overall long groove on the entire surface thereof. It is not necessary to limit it.

Looking at the manufacturing process of the VSMP according to the present invention configured as described above, first, the die 11 is attached to the chip mounting portion of the lead frame 13 using the insulating tape 14 separately fixed by the sawing process An attach process, a wire bonding process of electrically connecting and connecting the bond pad 11a of the die-attached chip 11 and the inner lead 12 of the lead frame 13 using the metal wire 15; In order to protect the finished chip 11 of the wire bonding process, the molding process of sealing using the epoxy molding compound 16, the trimming process of cutting the support bar 19 of the package after the molding process, and protruding out of the package The outlead 17 of the lead frame 13 is manufactured in the order of forming process of bending and inserting the outlead 17 of the molding line 16a into the outlead insertion groove 18 of the molding line 16a. Package as shown The plurality of outleads 17 exposed to one side are mounted by surface mount method (SMT) which contacts the metal lines (not shown) of the substrate 20 and then solders them as they are. By mounting on the substrate 20, a multi-chip module (MCM) is configured to expand memory capacity or perform other complex functions.

As described in detail above, the VSMP according to the present invention eliminates the process after the trimming / forming process, thereby reducing the manufacturing process and reducing the manufacturing cost, and the package generated due to the difference in thermal expansion coefficient because the paddle of the lead frame is removed. It not only prevents cracks, but also eliminates paddle margins, making it possible to produce lightweight and compact packages, reducing lead damage due to handling or mechanical impact during package manufacture, and mounting on surfaces. The height can be reduced, so that it can be applied to the module universally, and the chip occupied area of the package can be increased, so that it can be applied to large memory chips.

Claims (5)

In the semiconductor package structure, a semiconductor chip 11 having a plurality of bond pads 11a at both sides thereof, and an inner lead 12 connected to an external connection terminal of the semiconductor chip 11 are long, and a short chip A lead frame 13 manufactured in a lead form, an insulating tape 14 for attaching and fixing the semiconductor chip 11 to the lead frame 13, a bond pad 11a of the semiconductor chip 11, A plurality of metal wires 15 for electrically connecting and connecting the inner leads 12 of the lead frame 13, and an epoxy molding compound 16 for sealing to protect the wire bonded chip 11, The outlead insertion groove 18 into which the outlead 17 of the lead frame 13 which protrudes to the outside at the one side of the molding line 16a molded by the epoxy molding compound 16 is bent and inserted is formed, Vertical Small Mounting Package (VSMP) structure. 2. The lead frame 13 according to claim 1, wherein the short inner lead 12a and the long inner lead 12b are sequentially arranged, and at each end of each of the leads 12a and 12b, the substrate 20 is formed. Vertical small mounting package (VSMP) structure, characterized in that the outlead 17 for the connection with the extension is formed to a certain length and the support bar 19 is formed at the other end. The vertical small mounting package (VSMP) according to claim 2, wherein the inner lead 12 of the lead frame 13 is wire-bonded to both or one side of the bond pad 11a of the chip 11 mounted thereon. ) rescue. The vertical small mounting package (VSMP) structure according to claim 1, wherein the outlead insertion groove (18) formed at one side of the molding line (16a) is formed as a groove or an overall long groove of each of the leads (17). In the method of manufacturing a semiconductor package, a die attach step of attaching and fixing the chips 11 separately separated by a sawing step to the lead frame 13 using an insulating tape 14, and the die attached chips 11 Wire bonding process of connecting the bond pad 11a of the lead pad and the inner lead 12 of the lead frame 13 with the metal wire 15, and the epoxy molding compound to protect the chip 11 that has been wire-bonded. A molding process for sealing with the 16), a trimming process for cutting the support bar 19 of the package after the molding process, and an outlead 17 of the lead frame 13 protruding out of the package to the molding line 16a. Vertical small mounting package (VSMP) manufacturing method characterized in that it is produced, including a forming process to bend into the outlead insertion groove (18).