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KR940004850A - Thin film transistor and its manufacturing method - Google Patents

Thin film transistor and its manufacturing method Download PDF

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Publication number
KR940004850A
KR940004850A KR1019920014136A KR920014136A KR940004850A KR 940004850 A KR940004850 A KR 940004850A KR 1019920014136 A KR1019920014136 A KR 1019920014136A KR 920014136 A KR920014136 A KR 920014136A KR 940004850 A KR940004850 A KR 940004850A
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KR
South Korea
Prior art keywords
source
thin film
film transistor
semiconductor layer
substrate
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Application number
KR1019920014136A
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Korean (ko)
Inventor
손정하
배병성
김남덕
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019920014136A priority Critical patent/KR940004850A/en
Publication of KR940004850A publication Critical patent/KR940004850A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes

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  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 기판상에 형성된 게이트 전극, 상기 기판위에 게이트 전극을 절연하기 위하여 전면적으로 형성된 게이트 절연막, 상기 게이트 절연막위에 상기 게이트 전극보다 큰 길이로 형성된 반도체층, 및 소스/드레인 전극으로 이루어진 박막트랜지스터 및 그 제조 방법에 있어서, 상기 반도체층과 직접 접촉하는 소스 및 드레인 전극형성물질에 소량의 N형 불순물을 첨가시킴으로써 접촉 저항을 감소시킴과 동시에 종래 박막트랜지스터에서 문제가 되었던 오믹층 형성공정을 제거함으로써 공정수를 줄여서 공정 불량 및 원가절하에 기여할 수 있다.The present invention provides a thin film transistor comprising a gate electrode formed on a substrate, a gate insulating film formed entirely to insulate the gate electrode on the substrate, a semiconductor layer formed on the gate insulating film with a length greater than that of the gate electrode, and a source / drain electrode; In the manufacturing method, a small amount of N-type impurities are added to the source and drain electrode forming material in direct contact with the semiconductor layer to reduce the contact resistance and to remove the ohmic layer forming process, which has been a problem in the conventional thin film transistor. Reducing the number can contribute to process failure and cost reduction.

Description

박막트랜지스터 및 그의 제조방법Thin film transistor and its manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2(A) 및 (B)도는 본 발명에 따른 박막트랜지스터의 바람직한 실시예를 도시한 단면도이다.2 (A) and (B) are sectional views showing a preferred embodiment of the thin film transistor according to the present invention.

Claims (8)

기판상에 형성된 게이트 전극, 상기 기판위에 게이트 전극을 절연하기 위하여 전면적으로 형성된 게이트 절연막, 상기 게이트 절연막위에 상기 게이트 전극보다 큰 길이로 형성된 반도체층, 및 소스/드레인 전극으로 이루어진 박막트랜지스터의 제조 방법에 있어서, 상기 반도체층과 직접 접촉하는 소스/드레인 전극 형성물질에 소량의 불순물을 첨가하여 반도체층과의 접촉 저항을 감소시킨 소스/드레인 전극을 형성함을 특징으로 하는 박막 트랜지스터의 제조 방법.A method of manufacturing a thin film transistor comprising a gate electrode formed on a substrate, a gate insulating film formed entirely on the substrate to insulate the gate electrode on the substrate, a semiconductor layer formed on the gate insulating film with a length greater than the gate electrode, and a source / drain electrode. The method according to claim 1, wherein a small amount of impurities are added to the source / drain electrode forming material in direct contact with the semiconductor layer to form a source / drain electrode having a reduced contact resistance with the semiconductor layer. 제1항에 있어서, 상기 소스 및 드레인 전극은 N형 불순물이 극소량 첨가된 Cr금속으로 된 것을 특징으로 하는 박막트랜지스터의 제조 방법.The method of manufacturing a thin film transistor according to claim 1, wherein the source and drain electrodes are made of Cr metal to which a small amount of N-type impurities are added. 제1항에 있어서, 상기 소스 및 드레인 전극에 첨가된 불순물의 첨가량이 lwt％ 이하인 것을 특징으로 하는 박막트랜지스터의 제조 방법.The method of manufacturing a thin film transistor according to claim 1, wherein an addition amount of impurities added to the source and drain electrodes is 1 wt% or less. 제1항에 있어서, 상기 반도체층과 소스/드레인 전극 사이에 n+a-Si으로 이루어진 오믹층을 더 포함하는 것을 특징으로 하는 박막트랜지스터의 제조 방법.The method of claim 1, further comprising an ohmic layer made of n + a-Si between the semiconductor layer and the source / drain electrodes. 기판상에 형성된 게이트 전극, 상기 기판위에 게이트 전극을 절연하기 위하여 전면적으로 형성된 게이트 절연막, 상기 게이트 절연막위에 상기 게이트 전극보다 큰 길이로 형성된 반도체층, 및 소스/드레인 전극으로 이루어진 박막트랜지스터에 있어서, 상기 반도체층과 직접 접촉하는 소스 및 드레인 전극이 극소량의 N형 불순물이 첨가된 금속으로 된 것을 특징으로 하는 박막트랜지스터.A thin film transistor comprising a gate electrode formed on a substrate, a gate insulating film formed entirely on the substrate to insulate the gate electrode on the substrate, a semiconductor layer formed on the gate insulating film with a length greater than that of the gate electrode, and a source / drain electrode. A thin film transistor, characterized in that the source and drain electrodes in direct contact with the semiconductor layer are made of a metal to which a very small amount of N-type impurities are added. 제5항에 있어서, 상기 반도체층과 소스 및 드레인 전극 사이에 n+a-Si으로 구성된 오믹층을 더 포함하는 것을 특징으로 하는 박막트랜지스터.6. The thin film transistor of claim 5, further comprising an ohmic layer composed of n + a-Si between the semiconductor layer and the source and drain electrodes. 제5항에 있어서, 상기 반도체층과 소스 및 드레인 전극사이에 절연성 에치스토퍼층을 더 포함하는 것을 특징으로 하는 박막트랜지스터.6. The thin film transistor of claim 5, further comprising an insulating etch stopper layer between the semiconductor layer and the source and drain electrodes. 제5항에 있어서, 상기 소스 및 드레인 전극을 1wt％이하의 안티몬(Sb)이 첨가된 Cr 금속으로 된 것을 특징으로 하는 박막트랜지스터.The thin film transistor according to claim 5, wherein the source and drain electrodes are made of Cr metal to which antimony (Sb) of 1 wt% or less is added. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920014136A 1992-08-06 1992-08-06 Thin film transistor and its manufacturing method KR940004850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920014136A KR940004850A (en) 1992-08-06 1992-08-06 Thin film transistor and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920014136A KR940004850A (en) 1992-08-06 1992-08-06 Thin film transistor and its manufacturing method

Publications (1)

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KR940004850A true KR940004850A (en) 1994-03-16

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010094962A (en) * 2000-03-31 2001-11-03 포만 제프리 엘 Method of forming ohmic contacts using a self doping layer for thin-film transistors

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010094962A (en) * 2000-03-31 2001-11-03 포만 제프리 엘 Method of forming ohmic contacts using a self doping layer for thin-film transistors

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