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KR940003078Y1 - Stable bias current generating circuit - Google Patents

Stable bias current generating circuit Download PDF

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KR940003078Y1
KR940003078Y1 KR2019890011929U KR890011929U KR940003078Y1 KR 940003078 Y1 KR940003078 Y1 KR 940003078Y1 KR 2019890011929 U KR2019890011929 U KR 2019890011929U KR 890011929 U KR890011929 U KR 890011929U KR 940003078 Y1 KR940003078 Y1 KR 940003078Y1
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differential amplifier
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KR910005086U (en
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박상진
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금성일렉트론 주식회사
문정환
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements

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  • Power Engineering (AREA)
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Abstract

내용 없음.No content.

Description

안정화 바이어스전류 발생회로Stabilized Bias Current Generation Circuit

제1도는 종래의 바이어스전류 발생회로도.1 is a conventional bias current generating circuit diagram.

제2도는 본 고안의 안정화 바이어스전류 발생회로도.2 is a stabilized bias current generation circuit diagram of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 기준전류 발생부 20 : 제1하프커런트 발생부10: reference current generating unit 20: first half current generating unit

30 : 제2하프커런트 발생부 Q10-Q37;트랜지스터30: second half current generating unit Q10-Q37; transistor

R10-R15 : 저항R10-R15: Resistance

본 고안은 기준전류발생에 관한 것으로, 특히 변화에 따른 전압변화를 안정화시킬 수 있도록 한 안정화 바이어스전류 발생회로에 관한 것이다.The present invention relates to the generation of a reference current, and more particularly to a stabilization bias current generation circuit that can stabilize the voltage change according to the change.

제1도는 종래의 바이어스전류 발생회로도로서 이에 도시한 바와 같이, 트랜지스터(Q1,Q2)가 커렌트 미러(Current Mirror)로 구성되고, 트랜지스터(Q5)와 커렌트 미러로 구성되는 트랜지스터(Q4)의 베이스가 그 트랜지스터(Q4)의 콜렉터 및 상기 트랜지스터(Q2)의 콜렉터에 공통접속되어 구성되었다.FIG. 1 is a conventional bias current generation circuit diagram. As shown therein, transistors Q1 and Q2 are configured as current mirrors, and transistors Q5 and current mirrors of transistors Q4 are configured as current mirrors. The base was configured in common connection with the collector of the transistor Q4 and the collector of the transistor Q2.

이와같이 구성된 종래의 회로에 있어서, 트랜지스터(Q1)의 베이스-콜렉터에 흐르는 정전류를 Is라 할때, 그 트렌지스터(Q1)와 커렌트 미러를 형성하는 트랜지스터(Q2), (Q3)의 콜렉터에 각기 Is/2와 전류가 흐르게되고, 이에따라 상기 트랜지스터(Q2)의 콜렉터측에 커렌트 미러를 형성하는 트랜지스터(Q4), (Q5)의 콜렉터전류도 역시 Is/2의 전류가 흐르게되는데, 여기서 상기 트랜지스터(Q3), (Q5)의 전류방향은 서로 반대가 된다.In the conventional circuit configured as described above, assuming that the constant current flowing in the base-collector of the transistor Q1 is Is, each of the collectors of the transistors Q2 and Q3 forming the current mirror with the transistor Q1 is Is respectively. / 2 and a current flow, and accordingly, collector currents of transistors Q4 and Q5, which form a current mirror on the collector side of the transistor Q2, also flow a current of Is / 2, where the transistor ( The current directions of Q3) and Q5 are opposite to each other.

그러나 이와같은 종래의 회로에 있어서는 정전류원이 인가되는 트랜지스터의 베이스-에미터간 전압변동에 따라 정전류의 편차가 밸생되는 문제점이 있었다.However, in such a conventional circuit, there is a problem in that the variation of the constant current occurs due to the voltage variation between the base and the emitter of the transistor to which the constant current source is applied.

본 고안은 이와같은 종래의 문제점을 해결하기 위하여 전압변화에 관계없이 안정된 기준전류를 생성할 수 있는 회로를 안출한 것으로, 이를 첨부한 도면에 의하여 상세히 설명하면 다음과 같다.The present invention devised a circuit capable of generating a stable reference current regardless of voltage change in order to solve such a conventional problem, described in detail by the accompanying drawings as follows.

제2도는 본 고안의 안정화 바이어스전류 발생회로도로서 이에 도시한 바와같이, 기준전류(Is)를 발생하는 기준전류 발생부(10)와, 상기 기준전류 발생부(10)로 부터 입력되는 전류와 액티브로드(22) 및 궤환기(23)를 통해 공급되는 전류를 더하여 이를 차동증폭기(21)의 기준전류와 차동증폭함으로써Is 전류를 발생하는 제1하프커런트발생부(20)와, 상기 기준전류 발생부(10)로 부터 입력되는 전류와 액티브로드(32) 및 궤환기(33)를 통해 공급되는 전류를 더하여 이를 차동증폭기(31)의 기준전류와 차동증폭함으로서Is 전류를 발생하는 제2하프커런트발생부(30)로 구성한 것으로, 이와같이 구성된 본 고안의 작용 및 효과를 상세히 설명하면 다음과 같다.2 is a stabilized bias current generation circuit diagram of the present invention, as shown here, a reference current generator 10 for generating a reference current Is, and a current and active input from the reference current generator 10. By adding the current supplied through the load 22 and the feedback unit 23 and differentially amplifies it with the reference current of the differential amplifier 21 The first half current generating unit 20 generating the Is current, the current input from the reference current generating unit 10 and the current supplied through the active load 32 and the feedback unit 33 is added to the differential By differentially amplifying the reference current of the amplifier 31 The second half current generating unit 30 generating the Is current is described in detail as follows.

전류(11)가 소오싱(Sourcing)되지 않을때, 차동증폭용 트랜지스터(Q34,Q35)의 궤환작용에 의해 노드(N1)가 그라운드되는 상태에서, 바이어스관계를 살펴보면, 트랜지스터(Q32)의 베이스에서 트랜지스터(Q18)의 콜렉터간의 전위와, 그 트랜지스터(Q32)의 베이스에서 트랜지스터(Q27)의 베이스간의 전위가 같아야 하므로 VBE.Q29+VBE.Q28+(I1+I2)R14+R13×I2+VBE.Q27이 되고, △VBE.Q28+△I1×R14-△I2×R13-△VBE.Q27=0, △VBE.Q28+△I1×R14=△I2×R13+△VBE.Q27가 되는데, △VBE.Q28과 △VBE.Q27은 극히 작은 값이므로 무시할 수 없으며, 여기서 상기 저항(R13)를 통하는 전류(I2)값을 도출해낼 수 있다. 단, 여기서 트랜지스터(Q27)의 아이들링컨런트가 충분히 큰 것으로 가정하였다.In the state where the node N1 is grounded by the feedback of the differential amplification transistors Q34 and Q35 when the current 11 is not sourced, the bias relationship is found at the base of the transistor Q32. Since the potential between the collectors of the transistor Q18 and the base between the base of the transistor Q32 and the base of the transistor Q32 must be the same, V BE.Q29 + V BE.Q28 + (I 1 + I 2 ) R14 + R13 × I 2 + V BE.Q27 , ΔV BE.Q28 + ΔI 1 × R 14 -ΔI 2 × R 13 -ΔV BE.Q27 = 0, ΔV BE.Q28 + ΔI 1 × R 14 = ΔI 2 × R 13 + ΔV BE.Q27 , since ΔV BE.Q28 and ΔV BE.Q27 are extremely small values and cannot be ignored, where the value of current (I 2 ) through the resistor (R13) Can be derived. However, it is assumed here that the idling current of the transistor Q 27 is sufficiently large.

한편, 전류가 Is로 소오싱될때,On the other hand, when the current is sourced to Is,

VBE.Q32+VBE.Q31+△VBE.Q30+R15×I1 V BE.Q32 + V BE.Q31 + △ V BE.Q30 + R 15 × I 1

=VBE.Q29+VBE.Q28+△VBE.Q28+(I1+I2)R14+△I1×R14-△I2R13+I2×R13+△VBE.Q27-△VBE.Q27로 표현되고, 저항(R13)에서의 전류의 변화분을 △I2라 하고, 저항(R14)에서의 전류변화분을 △I1이라면, 노드(N1)에서,= V BE.Q29 + V BE.Q28 + DELTA V BE.Q28 + (I 1 + I 2 ) R 14 + ΔI 1 × R 14 -ΔI 2 R 13 + I 2 × R 13 + ΔV BE. Q27 -DELTA V BE . Q27 , if the change in current at the resistor R13 is ΔI 2 , and the change in current at the resistor R14 is ΔI 1, then at node N1,

Is+I2+I1-△I2=I1+I2+△I1 Is + I 2 + I 1- △ I2 = I 1 + I 2 + △ I 1

Is-△I2=△I2(단, △I2는 감소분으로 간주) Is- △ I 2 = △ I 2 ( However, △ I 2 is considered to decrease)

R13×(△I2)+△VBE.Q27=R14×△I1+△VBE.Q28가 되고, 여기서, 트랜지스터(Q27,Q28)의 베이스와 에미터간의 전압증감분을 서로 상쇄시키면,R13 × ( ΔI 2 ) + ΔV BE.Q27 = R14 × ΔI 1 + ΔV BE.Q28 , where the voltage increments between the base and emitter of transistors Q27 and Q28 cancel each other out.

R13×△I2=R14(Is-△I2)가 됨에 따라R13 × ΔI 2 = R14 (Is-ΔI2)

R13×△I2+R14×△I2=R14×IsR13 × ΔI 2 + R14 × ΔI2 = R14 × Is

∴△I2=IS가 되는 한편, 차동증폭용 트랜지스터(Q20,Q21)도 상기와 같은 동작으로 저항(R13)에서 △I2만큼 전류량이 감소될때 저항(R12)에서도 △I2만큼 전류량이 감소된다.∴ △ I2 = I S is the other hand, the transistor differential amplifier (Q20, Q21) which are also the same operation as the resistor (R13) △ I 2 by the amount of current is decreased in the resistance when the (R12) decreases in the △ I 2 by the amount of current.

여기서, 저항값이 R11=R12=R13=R14이면,Here, if the resistance value is R11 = R12 = R13 = R14,

△I2=가 되고, △I1=가 되므로 결국, 노드(N1)가 그라운드이기 때문에 증가전류 △I1에 의한 저항(R14)에서의 전압변화와, 감소전류 △I2에 대한 저항(13)에서의 전압변화가 안정화된다.△ I2 = ΔI1 = As a result, since the node N1 is ground, the voltage change at the resistor R14 caused by the increasing current? I 1 and the voltage change at the resistor 13 with respect to the decrease current? I2 are stabilized.

이상에서 상세히 설명한 바와같이 본 고안은 차동증폭기의 궤환작용을 이용하여 소오싱노드(Sourcing Node)를 그라운드로 함으로써 전압변화에 대한 전류변화를 안정화시키면서 기전전류를 형성시킬 수 있는 이점이 있다.As described in detail above, the present invention has an advantage in that a source current can be formed while stabilizing a current change with respect to a voltage change by setting a sourcing node to ground using the feedback action of the differential amplifier.

Claims (1)

안정화바이어스회로의 기준전류(Is)를 발생하는 기준전류 발생부(10)와, 상기 기준전류 발생부(10)로 부터 구동전원을 공급받고, 궤환기(23)를 통해 입력되는 전류를 기 설정된 전류와 차동증폭하는 차동증폭기(21), 상기 차동증폭기(21)의 구동에 따른 일정 전류를 발생하는 액티브 로드(22), 상기 액티브로드(22)의 출력전류를 상기 차동증폭기(21)의 일측 입력으로 궤환시키고, 외부로부터 공급되는 전류를 그 차동증폭기(21)의 일측 입력으로 공급하는 궤환기(23)로 구성되어 기준전류(Is)의 절반에 해당하는 전류(-Is/2)를 출력하는 제1하프커런트 발생부(20)와, 상기 기준전류 발생부(10)로 부터 구동전원을 공급받고, 궤환기(33)를 통해 입력되는 전류를 기 설정된 전류와 차동증폭하는 차동증폭기(31), 상기 차동증폭기(31)의 구동에 따른 일정 전류를 발생하는 액티브로드(32), 상기 액티브로드(32)의 출력전류를 상기 차동증폭기(31)의 일측 입력으로 궤환시키고, 외부로부터 공급되는 전류를 그 차동증폭기(31)의 일측 입력으로 궤환시키고, 외부로부터 공급되는 전류를 그 차동증폭기(31)의 일측 입력으로 공급하는 궤환기(33)로 구성되어 기준전류(Is)의 절반에 해당하는 전류(Is/2)를 출력하는 제2하프커런트발생부(30)로 구성한 것을 특징으로 하는 안정화 바이어스전류 발생회로.The reference current generator 10 generating the reference current Is of the stabilization bias circuit and the driving power are supplied from the reference current generator 10, and the current input through the feedback unit 23 is preset. The differential amplifier 21 differentially amplifies the current, the active load 22 generating a constant current according to the driving of the differential amplifier 21, and the output current of the active load 22 on one side of the differential amplifier 21. It consists of a feedback unit 23 which feeds back to the input and supplies the current supplied from the outside to one input of the differential amplifier 21, and outputs a current (-Is / 2) corresponding to half of the reference current Is. The first half current generating unit 20 and the differential current amplifier 31 receives the driving power from the reference current generating unit 10 and differentially amplifies the current input through the feedback unit 33 with the preset current. ), Acti to generate a constant current according to the drive of the differential amplifier 31 The broad current 32 and the output current of the active rod 32 are fed back to one input of the differential amplifier 31, and the current supplied from the outside is fed back to one input of the differential amplifier 31 and supplied from the outside. The second half current generating unit 30 is composed of a feedback unit 33 for supplying the current to the one side input of the differential amplifier 31 and outputs a current Is / 2 corresponding to half of the reference current Is. Stabilized bias current generation circuit, characterized in that consisting of).
KR2019890011929U 1989-08-12 1989-08-12 Stable bias current generating circuit Expired - Fee Related KR940003078Y1 (en)

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KR2019890011929U KR940003078Y1 (en) 1989-08-12 1989-08-12 Stable bias current generating circuit

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KR940003078Y1 true KR940003078Y1 (en) 1994-05-12

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020008377A (en) * 2001-11-14 2002-01-30 김재은 air gage wheel

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980055019A (en) * 1996-12-27 1998-09-25 김광호 Bias Circuit Compensates for Battery Supply Fluctuations

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020008377A (en) * 2001-11-14 2002-01-30 김재은 air gage wheel

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