[go: up one dir, main page]

KR940003040Y1 - Horizontal vertical dynamic focus circuit - Google Patents

Horizontal vertical dynamic focus circuit Download PDF

Info

Publication number
KR940003040Y1
KR940003040Y1 KR2019880019277U KR880019277U KR940003040Y1 KR 940003040 Y1 KR940003040 Y1 KR 940003040Y1 KR 2019880019277 U KR2019880019277 U KR 2019880019277U KR 880019277 U KR880019277 U KR 880019277U KR 940003040 Y1 KR940003040 Y1 KR 940003040Y1
Authority
KR
South Korea
Prior art keywords
voltage
capacitor
focus
transistor
resistor
Prior art date
Application number
KR2019880019277U
Other languages
Korean (ko)
Other versions
KR900011078U (en
Inventor
최종룡
Original Assignee
주식회사 금성사
최근선
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 금성사, 최근선 filed Critical 주식회사 금성사
Priority to KR2019880019277U priority Critical patent/KR940003040Y1/en
Publication of KR900011078U publication Critical patent/KR900011078U/en
Application granted granted Critical
Publication of KR940003040Y1 publication Critical patent/KR940003040Y1/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/16Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
    • H04N3/26Modifications of scanning arrangements to improve focusing

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Details Of Television Scanning (AREA)

Abstract

내용 없음.No content.

Description

수평 수직 다이나믹 포커스 회로Horizontal vertical dynamic focus circuit

제1도는 본 고안의 회로도.1 is a circuit diagram of the present invention.

제2도는 제1도에 따른 파형도.2 is a waveform diagram according to FIG.

제3도는 종래의 회로도.3 is a conventional circuit diagram.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 적분회로 C1-C7: 콘덴서10: integrating circuit C 1 -C 7 : condenser

D1,D2: 다이오드 FBT : 플라이백 트랜스D 1 , D 2 : Diode FBT: Flyback Trans

Q1,Q2: 트랜지스터 R1-R3: 저항Q 1 , Q 2 : transistor R 1 -R 3 : resistance

본 고안은 TV 모니터 등에 사용되는 CRT 화면의 수평수직 다이나믹 포커스 회로에 관한 것이다.The present invention relates to a horizontal and vertical dynamic focus circuit of a CRT screen used for a TV monitor.

종래의 CRT 포커스 회로는 제3도와 같이 입력단(S)에 트랜지스터(Q1), 콘덴서(C1)(C2), 다이오드(D1) 그리고 수평편향코일(L) 등이 접속된 플라이백 트랜스(FBT)의 출력단에 다이오드(D2)와 콘덴서(C3)그리고 가변저항(VR)을 통하여 CRT의 가속전압단자(G2)와 포커스 전압단자(G4)를 접속하여 구성되었다.The conventional CRT focus circuit has a flyback transformer in which a transistor Q 1 , a capacitor C 1 , a C 2 , a diode D 1 , a horizontal deflection coil L, and the like are connected to an input terminal S as shown in FIG. 3. The accelerating voltage terminal G 2 and the focus voltage terminal G 4 of the CRT are connected to the output terminal of the FBT via a diode D 2 , a capacitor C 3 , and a variable resistor VR.

이와 같이 구성된 종래의 회로에 있어서는 플라이백 트랜스(FBT)의 2차측 정류전압으로 CRT의 G2단자에 인가되는 전압을 가변저항(VR)을 이용하여 분배한 후 이를 CRT의 단자(G4)에 인가해 주므로 포커스 전압을 조정해줄 수 있었다.In the conventional circuit configured as described above, the voltage applied to the G 2 terminal of the CRT as the secondary rectified voltage of the flyback transformer (FBT) is distributed using the variable resistor VR, and then, the voltage is applied to the terminal G 4 of the CRT. It could be used to adjust the focus voltage.

그러나 종래에는 전자총에서 발생되는 전자가 CRT의 형광체에 부딪히는 거리가 CRT 중앙부분과 변두리부분과는 차이가 있기 때문에 이를 보상해 주기 위하여 포커스 전압을 변화시켜 주어야 했으나 전술한 바와 같이 포커스 전압이 CRT의 중심부분과 변두리 부분에 동일하게 인가되어 모든 부위의 포커스가 맞추어지지 않으므로 CRT 화면이 선명해지지 않게 되는 결점이 있었다.However, in the related art, since the distance from the electron gun to the phosphor of the CRT is different from the center and the edge of the CRT, the focus voltage has to be changed to compensate. However, as described above, the focus voltage is the center of the CRT. There was a drawback that the CRT screen would not be clear because it was applied equally to the part and the edge part, so that all parts were not focused.

본 고안은 이와 같은 종래의 결점을 감안하여 안출한 것으로 이를 첨부된 도면 제1도와 제2도에 의하여상술하면 다음과 같다.The present invention has been devised in view of the above-mentioned conventional drawbacks and will be described above with reference to FIGS. 1 and 2 of the accompanying drawings.

입력단(S)에 트랜지스터(Q1), 콘덴서(C1),(C2), 다이오드(D1) 그리고 수평편향코일(L)등이 접속된 플라이백 트랜스(FBT)의 출력단에 다이오드(D2)와 콘덴서(C8) 그리고 가변저항을 통하여 CRT의 가속전압단자(G2)와 포커스 전압단자(G4)를 접속하여서 된 것에 있어서, 상기 수평편향코일(L)과 콘덴서(C2)의 접점에 콘덴서 (C3)(C4)와 저항(R3)(R4)(R5)을 통하여 컬렉터에 저항(R5)을 매개하여 가속전압단자(G2)와 포커스 전압단자(G4)의 접점이 접속된 트랜지스터(Q2)의 베이스를 접속하고, 이 트랜지스터(Q2)의 에미터에는 저항 (R7)을 통하여 콘덴서(C7)와 플라이백 트랜스(FBT)의 일차측 접점과 가변저항(VR)을 접속하며, 상기 저항(R3)과 콘덴서(C4)의 접점에는 저항(R1-R3)과 콘덴서(C5)(C6)로 된 적분회로(10)를 접속하여 구성된 것으로, 도면중 미설명 부호 B+는 직류전원, 가-라는 각 점의 파형을 설명하기 위한 부호이다.The diode D is connected to the output terminal of the flyback transformer FBT in which the transistor Q 1 , the capacitor C 1 , C 2 , the diode D 1 , and the horizontal deflection coil L are connected to the input terminal S. 2 ), the capacitor C 8 and the accelerating voltage terminal G 2 and the focus voltage terminal G 4 of the CRT through the variable resistor, the horizontal deflection coil (L) and the capacitor (C 2 ) to the contact condenser (C 3) (C 4) and a resistor (R 3) (R 4) to mediate resistance (R 5) to the collector acceleration voltage terminal (G 2) and the focus voltage terminal via a (R 5) ( G 4 ) is connected to the base of the transistor Q 2 to which the contact is connected, and the emitter of this transistor Q 2 is connected to the capacitor C 7 and the flyback transformer FBT through the resistor R 7 . The secondary side contact and the variable resistor (VR) are connected, and an integrated circuit of resistors (R 1- R 3 ) and capacitors (C 5 ) (C 6 ) is connected to the contacts of the resistor (R 3 ) and the capacitor (C 4 ). 10) by connecting them, not shown in the figure Explanation code B + is a code for explaining the waveform of each point of DC power supply and ga-.

이와 같이 구성된 본 고안은 수직편향출력인 제2b도파형을 저항(R1), 콘덴서(C5)로 적분시키고 다시 저항 (R2), 콘덴서(C6)로 파형을 적분시키면서 저항(R3)으로 나오는 파형을 수직주기로 하여 파라볼라 파형이 되도록 하고, 수평편향코일(L)과 콘덴서(C2) 사이의 접점에서 생기는 파라볼라 파형 (가)와 콘덴서(C3) 및 저항(R8)을 거쳐 출력된 파라볼라 파형과 저항(R3)을 통해 출력되는 수직주기의 파라볼라 파형이 합쳐져서 생긴 (다)파형을 다시 콘덴서(C4)를 거쳐 크랜지스터(Q2)의 베이스에 인가시킨다.The present design constructed as is while integration of the vertical deflection output claim 2b waveguide type a resistance (R 1), a capacitor (C 5) and integrating the waveform back to the resistance (R 2), a capacitor (C 6) resistance (R 3 The parabolic waveform generated at the contact between the horizontal deflection coil (L) and the capacitor (C 2 ), the capacitor (C 3 ) and the resistor (R 8 ) The (C) waveform generated by combining the output parabola waveform and the parabolic waveform of the vertical period output through the resistor R 3 is applied to the base of the transistor Q 2 through the capacitor C 4 again.

이때, 트랜지스터(Q2)의 베이스 전압 레벨을 저항(R4)(R5)으로 조정하여 포커스 전압에서 원하는 다이나믹 포커스 전압의 파형 진폭을 정해줄 수 있다.At this time, the base voltage level of the transistor Q 2 may be adjusted with the resistors R 4 and R 5 to determine the waveform amplitude of the desired dynamic focus voltage at the focus voltage.

또한, 플라이백 트랜스(FBT)의 1차측에서 B+전압이 입력되는 위치에서 코일을 감아 콘덴서(C7)에 연결하므로 부스트업 전압을 발생시켜 발생된 양의 전압을 가변저항(VR)을 이용하여 저항(R7)을 거쳐 트랜지스터(Q2)의 에미터에 조정 가능한 전압을 인가시켜 준다.In addition, since the coil is wound at the position where the B + voltage is input at the primary side of the flyback transformer (FBT) and connected to the capacitor (C 7 ), a boost voltage is generated to generate a boost voltage to use the variable resistor (VR). An adjustable voltage is applied to the emitter of transistor Q 2 via resistor R 7 .

이때, 트랜지스터(Q2)의 베이스전압에 대한 트랜지스터(Q2)의 에미터 전압 조정에 따라 트랜지스터(Q2)의 컬렉터 전압의 전체 전압레벨 조정이 가능하여 포커스 전압 단자인 G4전압의 전체 전압 레벨 조정이 가능하다.At this time, the transistor (Q 2) the total voltage level can be adjusted to focus voltage terminal of the total voltage of the G 4 voltage of the collector voltage of the transistor (Q 2) in accordance with the emitter voltage adjustment of the transistor (Q 2) to the base voltage Level adjustment is possible.

즉, G2전압에서 저항(R6)을 통해 트랜지스터(Q2)의 컬렉터에 가해진 전압(이때의 파형은(라)이다)의 전체 전압 레벨 조정은 가변저항(VR) 조정으로 가능하고, 다이나믹 포커스 전압의 진폭 조정(높은 전압과 낮은 전압의 차이)은 저항(R4)(R5)선정으로 가능하다. 따라서 본 고안에서는 트랜지스터(Q2)의 컬렉터 전압 파형을 다이나믹 포커스 전압으로 사용한다.That is, the overall voltage level adjustment of the voltage applied at the collector of the transistor Q 2 through the resistor R 6 at the G 2 voltage (the waveform at this time is) is possible by the variable resistance VR adjustment. Amplitude adjustment (difference between high and low voltage) of the focus voltage is possible by selecting resistors R 4 and R 5 . Therefore, in the present invention, the collector voltage waveform of the transistor Q 2 is used as the dynamic focus voltage.

이상에서 설명한 바와 같은 본 고안은 포커스 볼륨저항(VR) 하나면 사용하여 CRT화면의 중심부분 및 가장자리 부분의 포커스를 최량으로 조절 가능하여 보다 선명한 CRT 화면을 얻을 수 있는 효과가 있다.As described above, the present invention has the effect of obtaining a clearer CRT screen by adjusting the focus of the central portion and the edge portion of the CRT screen to the maximum using one focus volume resistor (VR).

Claims (1)

수편편향코일(L)과 콘덴서(C2)의 접점에 콘덴서(C3)(C4)와 저항(R3)(R4)(R5)을 통하여 컬렉터에 가속전압단자(G2)와 포커스 전압단자(G4)의 접점이 접속된 트랜지스터(Q2)의 베이스를 접속하고, 이 트랜지스터의 에미터에는 콘덴서(C7)와 플라이백 트랜스(FBT)의 일차측 접점과 접속된 가변저항(VR)을 접속하여, 상기 저항(R8)과 콘덴서(C4)의 집점에는 적분회로(10)를 접속하여서 된 수평 수직 다이나믹 포커스 회로.Acceleration voltage terminal (G 2 ) and the collector through the capacitor (C 3 ) (C 4 ) and resistor (R 3 ) (R 4 ) (R 5 ) at the contact between the water deflection coil (L) and the capacitor (C 2 ) A variable resistor connected to the base of the transistor Q 2 to which the contact of the focus voltage terminal G 4 is connected, and the emitter of the transistor connected to the primary side contact of the capacitor C 7 and the flyback transformer FBT. A horizontal and vertical dynamic focus circuit connected by connecting (VR) to an integrating circuit (10) at a point of focus of the resistor (R 8 ) and the condenser (C 4 ).
KR2019880019277U 1988-11-29 1988-11-29 Horizontal vertical dynamic focus circuit KR940003040Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019880019277U KR940003040Y1 (en) 1988-11-29 1988-11-29 Horizontal vertical dynamic focus circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019880019277U KR940003040Y1 (en) 1988-11-29 1988-11-29 Horizontal vertical dynamic focus circuit

Publications (2)

Publication Number Publication Date
KR900011078U KR900011078U (en) 1990-06-04
KR940003040Y1 true KR940003040Y1 (en) 1994-05-11

Family

ID=19281650

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019880019277U KR940003040Y1 (en) 1988-11-29 1988-11-29 Horizontal vertical dynamic focus circuit

Country Status (1)

Country Link
KR (1) KR940003040Y1 (en)

Also Published As

Publication number Publication date
KR900011078U (en) 1990-06-04

Similar Documents

Publication Publication Date Title
US4547708A (en) Variable picture size circuit for a television receiver
US5323092A (en) Deflection waveform correction circuit
US5010281A (en) High voltage stabilization circuit for video display apparatus
US3444426A (en) Horizontal sweep system with automatic raster size regulation
EP0682446B1 (en) High voltage vertical dynamic focus amplifier
KR940003040Y1 (en) Horizontal vertical dynamic focus circuit
US4464612A (en) Circuit arrangement for a picture display device for generating a sawtooth-shaped line deflection current
US5463290A (en) Power supply stabilization circuit with separate AC/DC negative feedback paths
EP0251356A1 (en) Line deflection circuit in a picture display device
US5043638A (en) Dynamic focus adjusting voltage generating circuit
US4739228A (en) Electric circuit for S correction of the vertical scanning ramp in a television apparatus
US4187451A (en) Color picture display device with a circuit for generating a screen grid voltage
US4536682A (en) Circuit for generating a deflection current through the field deflection coil of a picture display device
US3723804A (en) Vertical deflection device utilizing rectifying means for deflection control
US5942861A (en) Front/back porch voltage-regulator of vertical focus control signal
CA2040252A1 (en) Parabolic voltage generating circuit
US3237048A (en) Raster distortion correction
US5633581A (en) Focusing voltage adjusting circuit and flyback transformer installing the same
KR900009592Y1 (en) Automatic focus circuit for tv
KR900005103Y1 (en) Focus control circuit of crt
GB2234132A (en) Sensed eht level controls brightness, contrast and therefore beam current
JP2696842B2 (en) High pressure stabilizer
KR800000901Y1 (en) Horizontal position adjustment circuit
JP2773323B2 (en) Dynamic focus voltage generation circuit
KR930002672Y1 (en) Screen grid stabilization circuit

Legal Events

Date Code Title Description
UA0108 Application for utility model registration

Comment text: Application for Utility Model Registration

Patent event code: UA01011R08D

Patent event date: 19881129

UG1501 Laying open of application
A201 Request for examination
UA0201 Request for examination

Patent event date: 19911128

Patent event code: UA02012R01D

Comment text: Request for Examination of Application

Patent event date: 19881129

Patent event code: UA02011R01I

Comment text: Application for Utility Model Registration

UG1604 Publication of application

Patent event code: UG16041S01I

Comment text: Decision on Publication of Application

Patent event date: 19940415

E701 Decision to grant or registration of patent right
UE0701 Decision of registration

Patent event date: 19940802

Comment text: Decision to Grant Registration

Patent event code: UE07011S01D

REGI Registration of establishment
UR0701 Registration of establishment

Patent event date: 19940819

Patent event code: UR07011E01D

Comment text: Registration of Establishment

UR1002 Payment of registration fee

Start annual number: 1

End annual number: 3

Payment date: 19940819

UR1001 Payment of annual fee

Payment date: 19961211

Start annual number: 4

End annual number: 4

UR1001 Payment of annual fee

Payment date: 19971227

Start annual number: 5

End annual number: 5

FPAY Annual fee payment

Payment date: 19981216

Year of fee payment: 6

UR1001 Payment of annual fee

Payment date: 19981216

Start annual number: 6

End annual number: 6

LAPS Lapse due to unpaid annual fee
UC1903 Unpaid annual fee