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KR940001162A - Booster of Semiconductor Memory - Google Patents

Booster of Semiconductor Memory Download PDF

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KR940001162A
KR940001162A KR1019920011242A KR920011242A KR940001162A KR 940001162 A KR940001162 A KR 940001162A KR 1019920011242 A KR1019920011242 A KR 1019920011242A KR 920011242 A KR920011242 A KR 920011242A KR 940001162 A KR940001162 A KR 940001162A
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voltage
node
pumping
boosting
circuit
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KR950004559B1 (en
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최도찬
석용식
이동재
전동수
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김광호
삼성전자 주식회사
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Priority to KR1019920011242A priority Critical patent/KR950004559B1/en
Priority to ITMI922545A priority patent/IT1258242B/en
Priority to DE4244992A priority patent/DE4244992B4/en
Priority to FR9213411A priority patent/FR2689294B1/en
Priority to DE4237589A priority patent/DE4237589C2/en
Priority to JP4298831A priority patent/JP2604526B2/en
Priority to GB9511378A priority patent/GB2288678B/en
Priority to US07/972,780 priority patent/US5367489A/en
Priority to GB9223478A priority patent/GB2261307B/en
Priority to TW081109123A priority patent/TW273059B/zh
Publication of KR940001162A publication Critical patent/KR940001162A/en
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Publication of KR950004559B1 publication Critical patent/KR950004559B1/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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Abstract

본 발명은, 소정레벨의 승압전압을 사용하는 회로들을 가지는 반도체 메모리장치에 있어서. 상기 승압전압을 사용하는 회로에 연결된 승압노드와, 파워엎싸이클동안 소정레벨의 펌핑전압을 발생하는 펌핑회로와, 상기 펌핑 전압에 응답하여 상기 펌핑전압을 상기 승압노드로 전송하는 아이솔레이션수단과, 삽기 승압전압을 사용하는 회로로부터 출력되는 신호에 응답하여 상기 승압전압의 소정레벨의 강하분만큼 상기 승압전압의 레벨을 보상시키는 액티브킥커와, 상기 승압노드의 현재의 전위상태에 응답하는 감지신호를 최소한 상기 펌핑회로로 궤환시키는 디텍터와, 상기 감지신호를 입력하여 상기 승압전압의 소정레벨의 상승분만큼 상기 승압전압을 강하시키는 클램퍼를 구비하는 반도체메모리장치를 제공한다.The present invention provides a semiconductor memory device having circuits that use a boost voltage of a predetermined level. A boosting node connected to the circuit using the boosting voltage, a pumping circuit for generating a pumping voltage of a predetermined level during a power up cycle, isolation means for transmitting the pumping voltage to the boosting node in response to the pumping voltage, and a shovel An active kicker for compensating the level of the boosted voltage by a drop of the predetermined level of the boosted voltage in response to a signal output from a circuit using the boosted voltage, and at least a sensing signal corresponding to a current potential state of the boosted node. A detector for feeding back to the pumping circuit and a clamper for inputting the sensing signal to lower the boosted voltage by an increase of a predetermined level of the boosted voltage are provided.

Description

반도체메모리의 승압장치Booster of Semiconductor Memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 승압장치의 블럭다이어그램,3 is a block diagram of a boosting device according to the present invention,

제8도는 본 발명에 따른 Vpp의 발생 및 보상동작을 보여주는 전압파형도.8 is a voltage waveform diagram showing the generation and compensation operation of Vpp according to the present invention.

Claims (19)

소정레벨의 승압전압을 사용하는 회로들을 가지는 반도체메모리장치에 있어서, 상기 승압전압을 사용하는 회로에 연결된 승압노드와, 파워엎싸이클동안 소정레벨의 펌핑전압을 발생하는 펌핑회로와, 상기 펌핑전압에 응답하여 상기 펌핑전압을 상기 승압노드로 전송하는 아이솔레이션수단과, 상기 승압전압을 사용하는 회로로부터 출력되는 신호에 응답하여 상기 승압전압의 소정레벨의 강하분만큼 상기 승압전압의 레벨을 보상시키는 액티브킥커와, 상기 승압노드의 현제의 전위상태에 응답하는 감지신호를 최소한 상기 펌핑회로로 궤환시키는 디텍터와, 상기 감지신호를 입력하여 상기 승압전압의 소정레벨의 상승분만큼 상기 승압전압을 강하시키는 클램퍼를 구비함을 특징으로 하는 반도체메모리장치,A semiconductor memory device having circuits using a boosted voltage of a predetermined level, the semiconductor memory device comprising: a boosting node connected to the boosted voltage; a pumping circuit for generating a pumping voltage of a predetermined level during a power cycle; Isolating means for transmitting the pumping voltage to the boosting node in response, and an active kicker for compensating the level of the boosting voltage by a predetermined drop of the boosting voltage in response to a signal output from a circuit using the boosting voltage. And a detector for returning a sensing signal in response to a current potential state of the boosting node to the pumping circuit at least, and a clamper for inputting the sensing signal to lower the boosting voltage by an increase of a predetermined level of the boosting voltage. Semiconductor memory device, characterized in that 제1항에 있어서, 상기 펌핑회로가 전원전압과 상기 감지신호의 상태들에 따라 펌핑클럭을 발생하는 오실레이터와, 각각 제1 및 제2펌핑노드를 가지며 상기 펌핑클럭에 응답하여 서로 상보적으로 동작하는 제1 및 제2차아지펌프를 구비함을 특징으로 하는 반도체메모리장치.The pumping circuit of claim 1, wherein the pumping circuit has an oscillator for generating a pumping clock according to power supply voltages and states of the sensing signal, and first and second pumping nodes, respectively, and are complementary to each other in response to the pumping clock. And a first charge pump and a second charge pump. 제2항에 있어서, 상기 아이솔레이션수단이, 게이트가 상기 제2펌핑노드에 접속되고 채널이 상기 제2펌핑노드와 상기 승압노드 사이에 접속된 제1아이솔레이션트랜지스터와, 게이트가 상기 제2펌핑노드에 접속되고 채널이 상기 제2펌핑노드와 상기 승압노드 사이에 접속된 제2아이솔레이션트랜지스터로 구성됨을 특징으로 하는 반도체메모리장치.3. The device of claim 2, wherein the isolation means comprises: a first isolation transistor having a gate connected to the second pumping node and a channel connected between the second pumping node and the boosting node; and a gate connected to the second pumping node. And a second isolation transistor connected to the channel and connected between the second pumping node and the boosting node. 제3항에 있어서, 상기 제1및 제2펌핑노드의 전위를 미리 소정레벨로 설정하여 주는 프리차아지회로를 더 구비함을 특징으로 하는 반도체메모리장치.4. The semiconductor memory device according to claim 3, further comprising a precharge circuit for setting potentials of the first and second pumping nodes to predetermined levels in advance. 제1항에 있어서, 상기 승압노드의 전위를 미리 소정레벨로 설정하여 주는 프리차아지회로를 더 구비함을 특징으로 하는 반도체메모리장치.2. The semiconductor memory device according to claim 1, further comprising a precharge circuit for setting the potential of the boosting node to a predetermined level in advance. 제1항에 있어서, 상기 액티브킥커가, 상기 전원전압과 상기 승압전압을 사웅하는 회로로부터 출력되는 복수개의 신호를 입력하는 논리게이트와, 킥킹노드와, 상기 논리게이트의 풀력전위가 제1상태일때 상기 킥킹노드의 전위를 제1레벨로 설정하여 주는 프리킥커와, 상기 논리게이트의 출력전위가 제2상태일때 상기 킥킹노드의 전위를 상기 제1레벨로부터 제2레벨로 끌어올리는 킥킹드라이버와, 상기 킥킹노드와 상기 승압노드사이에 채널이 연결되고 상기 킥킹노드의 전위에 응답하는 제3아이솔레이션트랜지스터를 구비함을 특징으로 하는 반도체메모리장치.The logic circuit of claim 1, wherein the active kicker comprises: a logic gate configured to input a plurality of signals output from the circuit for power supply and the boosted voltage; a kicking node; and a pull potential of the logic gate in a first state. A free kicker for setting the potential of the kicking node to the first level; a kicking driver for raising the potential of the kicking node from the first level to the second level when the output potential of the logic gate is in the second state; And a third isolation transistor connected between a kicking node and the boosting node and responsive to a potential of the kicking node. 제1항에 있어서, 상기 클램퍼가 상기 감지신호의 전위상태에 따라 제어되고, 상기 승압전압과 전원전압사이에 직렬로 형성된 직류패스의 가짐을 특징으로 하는 반도체메모리장치.2. The semiconductor memory device according to claim 1, wherein said clamper is controlled in accordance with the potential state of said sensing signal and has a direct current path formed in series between said boost voltage and a power supply voltage. 제1항에 있어서, 상기 클램퍼가상기 승압전압과 전원전압사이에 직렬로 형성된 직류패스의 가짐을 특징으로 하는 반도체메모리장치.The semiconductor memory device according to claim 1, wherein the clamper has a direct current path formed in series between the boosted voltage and the power supply voltage. 펌핑수단을 이용하여 소정레벨의 승압된 전압을 승압전압을 사용하는 회로로 공급하기 위한 승압장치에 있어서, 상기 펌핑수단과 상기 승압전압이 필요한 회로사이에 연결되고 상기 펌핑수단에 의해 만들어진 펌핑 전압에 응답하여 상기 펌핑전압을 상기 승압전압을 사용하는 회로로 전송하는 제1스위칭수단과, 전압킥킹수단들을 가지고 상기 승압전압을 사용하는 회로의 출력측과 입력측사이에 연결되어 상기 승압전압을 사용하는 회로로부터 출력되는 신호들의 상태에 따라 상기 전압킥킹수단들에 의해 만들어진 킥킹전압을 상기 승압전압을 사용하는 회로로 전송하는 제2스위칭수단을 구비함을 특징으로 하는 승압장치.A boosting device for supplying a boosted voltage of a predetermined level to a circuit using a boosting voltage by using a pumping means, the boosting device being connected between a pumping means and a circuit requiring a boosting voltage, First switching means for transmitting the pumping voltage to the circuit using the boosted voltage in response, and between the output side and the input side of the circuit using the boosted voltage with voltage kicking means and using the boosted voltage. And a second switching means for transmitting the kicking voltage generated by the voltage kicking means to a circuit using the boosting voltage according to the state of the output signals. 제9항에 있어서, 상기 제1스위칭수단이, 상기 펌핑전압과 상기 승압전압을 사용하는 회로사이에 채널이 연결되고 상기 펌핑전압에 게이트가 접속된 절연게이트 전계효과트랜지스터로 이루어짐을 특징으로 하는 승압장치.10. The boosting method of claim 9, wherein the first switching means comprises an insulated gate field effect transistor having a channel connected between the pumping voltage and a circuit using the boosting voltage and a gate connected to the pumping voltage. Device. 제9항또는 제10항에 있어서, 제2스위칭수단이, 상기킥킹전압과 상기 승압전압을 사용하는 회로상이 채널이 연결되고 상기 킥킹전압에 게이트가 접속된 절연게이트 전제효과트랜지스터로 이루어짐을 특징으로 하는 승압 장치.11. The method of claim 9 or 10, characterized in that the second switching means comprises an insulated gate pre-effect transistor having a channel connected to the circuit using the kicking voltage and the boosted voltage and a gate connected to the kicking voltage. Boosting device. 복수개의 메모리셀들과, 상기 복수개의 메모리셀들의 각각에 연결된 복수개의 워드라인들과, 상기 복수개의 메모리셀들의 각각에 연결된 복수개의 비트라인들과, 상기 복수개의 비트라인들에 대응하는 복수개의 입출력 라인들과, 상기 한쌍의 비트라인 사이에 각각 연결되어 상기 비트라인쌍사이의 전위차를 중폭하는 복수개의 센스 앰프들과, 상기 비트라인들과 입출력 라인들 사이에 연결된 복수개의 분리게이트들과, 상기 워드라인들을 선택하는 복수개의 워드라인드라이버드를 가지는 반도체메모리장치에 있어서, 상기 승압전압을 사용하는 회로에 연결된 승압노드와, 파워엎싸이클동안 소정레벨의 펌핑전압을 발생하는 펌핑회로와, 상기 펌핑전압에 응답하여 상기 펌핑전압을 상기 승압노드로 전송하는 아이솔레이션수단과, 상기 승압전압을 사용하는 회로로부터 출력되는 신호에 응답하여 상기 승압전압의 소정제벨의 강하분만큼 상기 승압전압의 레벨을 보상시키는 액티브킥커와, 상기 승압노드의 현제의 전위상태에 응답하는 감지신호를 최소한 상기 승압전압의 소정레벨의 상승분만큼 상기 승압전압을 강하시키는 클램퍼를 구비함을 특징으로 하는 반도체메모리장치.A plurality of memory cells, a plurality of word lines connected to each of the plurality of memory cells, a plurality of bit lines connected to each of the plurality of memory cells, and a plurality of bit lines corresponding to the plurality of bit lines A plurality of sense amplifiers connected between the input / output lines and the pair of bit lines, respectively, to reduce the potential difference between the pair of bit lines, a plurality of separation gates connected between the bit lines and the input / output lines, A semiconductor memory device having a plurality of word line drivers for selecting the word lines, comprising: a boost node connected to a circuit using the boost voltage, a pumping circuit generating a pumping voltage of a predetermined level during a power cycle; Isolation means for transmitting the pumping voltage to the boosting node in response to a pumping voltage; An active kicker for compensating for the level of the boosted voltage by a predetermined drop of the boosted voltage in response to a signal output from the circuit; and a sensing signal corresponding to a current potential state of the boosted node at least the boosted voltage. And a clamper for lowering the boosted voltage by an increase of a predetermined level of the semiconductor memory device. 제12항에 있어서, 상기 평핑회로가 전원전압과 상기 감지신호의 상태들에 따라 펌핑클럭을 발생하는 오실레이터와, 각각 제1 및 제2차아지펌프를 구비함을 특징으로 하는 반도체메모리장치,13. The semiconductor memory device according to claim 12, wherein the flattening circuit comprises an oscillator for generating a pumping clock in accordance with power supply voltages and states of the detection signal, and first and second charge pumps, respectively. 제13항에 있어서, 상기 아이솔레이션수단이, 게이트가 상기 제1펌핑노드에 접속되고 채널이 상기 제1펌핑 노드와 상기 승압노드사이에 접속된 제2아이솔레이션트랜지스터와, 게이트가 상기 제2펑핑노드에 접속되고 채널이 상기 제2펌핑노드와 상기 승압노드사이에 접속된 제2아이솔레이션트랜지스터로 구성됨을 특징으로 하는 반도체메모리장치.14. The apparatus of claim 13, wherein the isolation means comprises: a second isolation transistor having a gate connected to the first pumping node and a channel connected between the first pumping node and the boosting node; and a gate connected to the second popping node. And a second isolation transistor connected to the channel and connected between the second pumping node and the boosting node. 제14항에 있어서, 상기 제1 및 제2펌핑노드의 전위를 미리 소정레벨로 설정하여 주는 프리아차지회로를 더 구비함을 특징으로 하는 반도체메모리장치.15. The semiconductor memory device according to claim 14, further comprising a precharge circuit for setting potentials of the first and second pumping nodes to predetermined levels in advance. 제12항에 있어서, 상기 승압노드의 전위를 미리 소정레벨로 설정하여 주는 프리차아지회로를 더 구비함을 특징으로 하는 반도체메모리장치.13. The semiconductor memory device according to claim 12, further comprising a precharge circuit for setting the potential of the boosting node to a predetermined level in advance. 제12항에 있어서, 상기 액티브킥커가, 상기 전원전압과 상기 승압전압을 사용하는 회로로부터 출력되는 복수개의 신호를 입력하는 논리게이트와, 킥킹노드와, 상기 논리게이트의 출력전위가 제1상태일때 상기 킥킹노드의 전위를 제 1레벨로 설정하여 주는 프리킥커와, 상기 논리게이트의 출력전위가 제2상태 일때 상기 킥킹노드의 전위를 상기 제1레벨로부터 제2레벨로 끌어올리는 킥킹드라이버와, 상기 킥킹노드와 상기 승압노드사이에 채널이 연결되고 상기 킥킹노드의 전위에 응답하는 제3아이숄레이션트랜지스터를 구비함을 특징으로 하는 반도체메모리장치.The logic circuit of claim 12, wherein the active kicker comprises: a logic gate configured to input a plurality of signals output from a circuit using the power supply voltage and the boosted voltage; a kicking node; and an output potential of the logic gate is in a first state. A free kicker for setting the potential of the kicking node to the first level; a kicking driver for raising the potential of the kicking node from the first level to the second level when the output potential of the logic gate is in the second state; And a third eye isolation transistor connected between a kicking node and the boosting node and responsive to a potential of the kicking node. 제12항에 있어서, 상기 클램퍼가 상기 감지신호의 전위상태에 따라 제어되고, 상기 승압전압과 전원전압사이에 직렬로 형성된 직류패스를 가짐을 특징으로 하는 반도체메모리장치.13. The semiconductor memory device according to claim 12, wherein the clamper is controlled in accordance with the potential state of the sense signal and has a direct current path formed in series between the boosted voltage and the power supply voltage. 제12항에 있어서, 상기 클램퍼가 상기 승압전압과 전원전압사이에 직렬로 형성된 직류패스를 가짐을 특징으로 하는 반도체메모리장치.13. The semiconductor memory device according to claim 12, wherein the clamper has a direct current path formed in series between the boosted voltage and the power supply voltage. ※ 참고사항：최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920011242A 1991-11-07 1992-06-26 Boosting device of semiconductor memory Expired - Fee Related KR950004559B1 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
KR1019920011242A KR950004559B1 (en) 1992-06-26 1992-06-26 Boosting device of semiconductor memory
ITMI922545A IT1258242B (en) 1991-11-07 1992-11-05 SEMICONDUCTOR MEMORY DEVICE INCLUDING SUPPLY VOLTAGE PUMPING CIRCUIT
FR9213411A FR2689294B1 (en) 1991-11-07 1992-11-06 VOLTAGE PUMPING CIRCUIT FOR USE IN SEMICONDUCTOR MEMORY DEVICES.
DE4237589A DE4237589C2 (en) 1991-11-07 1992-11-06 Voltage pump circuit
DE4244992A DE4244992B4 (en) 1991-11-07 1992-11-06 Semiconductor memory device with voltage pumping circuit - comprises oscillator for generating pulses, and voltage pumping circuit for generating at initial power-up state, first output voltage equal to supply voltage
GB9511378A GB2288678B (en) 1991-11-07 1992-11-09 Voltage pumping circuits
JP4298831A JP2604526B2 (en) 1991-11-07 1992-11-09 Semiconductor memory device
US07/972,780 US5367489A (en) 1991-11-07 1992-11-09 Voltage pumping circuit for semiconductor memory devices
GB9223478A GB2261307B (en) 1991-11-07 1992-11-09 Semiconductor memory device including voltage pumping circuit
TW081109123A TW273059B (en) 1991-11-07 1992-11-14

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KR1019920011242A KR950004559B1 (en) 1992-06-26 1992-06-26 Boosting device of semiconductor memory

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KR950004559B1 KR950004559B1 (en) 1995-05-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102120039B1 (en) 2019-03-08 2020-06-09 주식회사 로벤 Sterilization apparatus for vending machine of ice drinking water

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102120039B1 (en) 2019-03-08 2020-06-09 주식회사 로벤 Sterilization apparatus for vending machine of ice drinking water

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