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KR930011242A - Static memory - Google Patents

Static memory Download PDF

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Publication number
KR930011242A
KR930011242A KR1019920021722A KR920021722A KR930011242A KR 930011242 A KR930011242 A KR 930011242A KR 1019920021722 A KR1019920021722 A KR 1019920021722A KR 920021722 A KR920021722 A KR 920021722A KR 930011242 A KR930011242 A KR 930011242A
Authority
KR
South Korea
Prior art keywords
circuit
potential
selection signal
bit line
data
Prior art date
Application number
KR1019920021722A
Other languages
Korean (ko)
Other versions
KR960012058B1 (en
Inventor
아즈마 스즈키
마사다카 마츠이
Original Assignee
사또오 후미오
가부시기가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 사또오 후미오, 가부시기가이샤 도시바 filed Critical 사또오 후미오
Publication of KR930011242A publication Critical patent/KR930011242A/en
Application granted granted Critical
Publication of KR960012058B1 publication Critical patent/KR960012058B1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

내용없음No content

Description

스태틱형 메모리Static memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 SRAM의 일예를 나타낸 회로도.1 is a circuit diagram showing an example of a conventional SRAM.

제 2 도는 요부를 나타낸 회로도.2 is a circuit diagram showing the main parts.

제3도는 본 발명의 제1의 실시예를 나타낸 회로도.3 is a circuit diagram showing a first embodiment of the present invention.

제4도는 제3도에 나타낸 회로의 동작을 설명하기 위해 나타낸 타이밍차트.4 is a timing chart shown for explaining the operation of the circuit shown in FIG.

제5도는 본 발명의 제2의 실시예를 나타낸 회로도.5 is a circuit diagram showing a second embodiment of the present invention.

제6도는 제5도에 나타낸 회로의 동작을 설명하기 위해 나타낸 다이밍차트.FIG. 6 is a dimming chart shown to explain the operation of the circuit shown in FIG.

제7도는 본 발명의 제3의 실시예를 나타낸 회로도.7 is a circuit diagram showing a third embodiment of the present invention.

제8도는 제7도에 나타낸 회로의 동작을 설명하기 위해 나타낸 타이밍차트.8 is a timing chart shown to explain the operation of the circuit shown in FIG.

제9도는 비트선 전위를 생성하는 회로의 변형예를 나타낸 회로도.9 is a circuit diagram showing a modification of the circuit for generating a bit line potential.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 메모리 셀 12 : 비트선 부하 회로11 memory cell 12 bit line load circuit

23 : SWE(섹션 라이트 인에이블) 신호 발생 회로23: SWE (section light enable) signal generation circuit

31 : 비트선 전위 공급 회로 BL,/BL : 비트선31: bit line potential supply circuit BL, / BL: bit line

Claims (4)

복수의 비트선쌍(BL,/BL)과 복수의 워드선과의 각 교차 위치에 스태틱형 메모리 셀(11)이 배설되며, 복수의 스태틱형 메모리 셀마다 섹션으로 된 메모리 셀 어레이와, 데이타의 기록 및 독출 동작에 따라, 상기 섹션을 선택하기 위한 선택 신호(SWE)를 생성하는 선택 신호 생성 회로와, 하이 레벨의 제1, 제2의 전위를 생성하여 상기 선택 신호 생성 회로에서 출력되는 선택 신호에 따라 제1, 제2의 전위를 선택하여 상기 비트선쌍에 공급하는 전위 생성 회로(31)를 구비하는 것을 특징으로 하는 스태틱형 메모리.A static memory cell 11 is disposed at each intersection between a plurality of bit line pairs BL, / BL and a plurality of word lines, and each memory cell array is divided into sections for each of the plurality of static memory cells, and data is written and According to a read operation, a selection signal generation circuit for generating a selection signal SWE for selecting the section, and a first and second potentials of high levels are generated and output according to the selection signal output from the selection signal generation circuit. And a potential generating circuit (31) which selects first and second potentials and supplies them to the pair of bit lines. 제1항에 있어서, 상기 전위 생성 회로는 선택 신호에 따라 데이타의 기록시에 제1의 전위를 비트선 쌍에 공급하고, 데이타의 독출시에 제2의 전위를 비트선쌍에 공급하는 회로를 갖는 것을 특징으로 하는 스태틱형 메모리.2. The circuit according to claim 1, wherein the potential generating circuit has a circuit for supplying a first potential to the bit line pair when data is written and a second potential to the bit line pair when data is read in accordance with a selection signal. Static type memory, characterized in that. 제1항에 있어서, 상기 전위 생성 회로는 선택 신호에 따라 데이타의 독출시만 소정 기간 제1의 전위를 비트선쌍에 공급하는 회로를 갖는 것을 특징으로 하는 스태틱형 메모리.2. The static memory according to claim 1, wherein said potential generating circuit has a circuit for supplying a first potential to a pair of bit lines for a predetermined period only when data is read in accordance with a selection signal. 제1항에 있어서, 상기 전위 생성 회로는 선택 신호에 따라 데이타의 독출시에 소정 기간 제1의 전위를 비트선쌍에 공급한 다음, 제2의 전위를 비트선쌍에 공급하는 회로를 갖는 것을 특징으로 하는 스태틱형 메모리.2. The circuit according to claim 1, wherein the potential generating circuit has a circuit for supplying a first potential to the bit line pair for a predetermined period when data is read in accordance with a selection signal, and then supplying a second potential to the bit line pair. Static type memory. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920021722A 1991-11-21 1992-11-19 Static memory KR960012058B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP03305978A JP3110113B2 (en) 1991-11-21 1991-11-21 Static memory
JP91-305978 1991-11-21

Publications (2)

Publication Number Publication Date
KR930011242A true KR930011242A (en) 1993-06-24
KR960012058B1 KR960012058B1 (en) 1996-09-11

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920021722A KR960012058B1 (en) 1991-11-21 1992-11-19 Static memory

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US (1) US5309401A (en)
JP (1) JP3110113B2 (en)
KR (1) KR960012058B1 (en)

Families Citing this family (16)

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Publication number Priority date Publication date Assignee Title
JP3011570B2 (en) * 1993-04-30 2000-02-21 株式会社東芝 Semiconductor memory
US5440524A (en) * 1994-02-01 1995-08-08 Integrated Device Technology, Inc. Method and apparatus for simuilataneous long writes of multiple cells of a row in a static ram
US5396469A (en) * 1994-03-31 1995-03-07 Hewlett-Packard Company SRAM memory requiring reduced voltage swing during write
JP3404127B2 (en) * 1994-06-17 2003-05-06 富士通株式会社 Semiconductor storage device
JP4198201B2 (en) * 1995-06-02 2008-12-17 株式会社ルネサステクノロジ Semiconductor device
JP3606951B2 (en) * 1995-06-26 2005-01-05 株式会社ルネサステクノロジ Semiconductor memory device
US5844852A (en) * 1995-11-16 1998-12-01 Intel Corporation Memory arrays with integrated bit line voltage stabilization circuitry
KR0172345B1 (en) * 1995-11-27 1999-03-30 김광호 Data output control circuit of hyper page mode
JP3537010B2 (en) * 1995-11-28 2004-06-14 シャープ株式会社 Semiconductor storage device
US5757713A (en) * 1996-09-18 1998-05-26 Micron Technology, Inc. Adjustable write voltage circuit for SRAMS
US5999469A (en) * 1998-03-04 1999-12-07 Lsi Logic Corporation Sense time reduction using midlevel precharge
US6335891B1 (en) 1999-02-25 2002-01-01 Micron Technology, Inc. Device and method for reducing standby current in a memory device by disconnecting bit line load devices in unused columns of the memory device from a supply voltage
JP2004295950A (en) 2003-03-25 2004-10-21 Ricoh Co Ltd Optical information recording medium, optical information recording device, information processing device, optical information recording method, program, and storage medium
JP3920827B2 (en) * 2003-09-08 2007-05-30 三洋電機株式会社 Semiconductor memory device
JP2009064512A (en) * 2007-09-06 2009-03-26 Panasonic Corp Semiconductor memory device
US7760576B2 (en) * 2007-11-08 2010-07-20 Qualcomm Incorporated Systems and methods for low power, high yield memory

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US4961168A (en) * 1987-02-24 1990-10-02 Texas Instruments Incorporated Bipolar-CMOS static random access memory device with bit line bias control
US4947374A (en) * 1987-05-12 1990-08-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor memeory device in which writing is inhibited in address skew period and controlling method thereof
US5046052A (en) * 1988-06-01 1991-09-03 Sony Corporation Internal low voltage transformation circuit of static random access memory
US4975877A (en) * 1988-10-20 1990-12-04 Logic Devices Incorporated Static semiconductor memory with improved write recovery and column address circuitry
JP2981263B2 (en) * 1990-08-03 1999-11-22 富士通株式会社 Semiconductor storage device

Also Published As

Publication number Publication date
US5309401A (en) 1994-05-03
KR960012058B1 (en) 1996-09-11
JP3110113B2 (en) 2000-11-20
JPH05145039A (en) 1993-06-11

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