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KR930011238A - Memory cell of static RAM and memory cell array - Google Patents

Memory cell of static RAM and memory cell array Download PDF

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Publication number
KR930011238A
KR930011238A KR1019920020846A KR920020846A KR930011238A KR 930011238 A KR930011238 A KR 930011238A KR 1019920020846 A KR1019920020846 A KR 1019920020846A KR 920020846 A KR920020846 A KR 920020846A KR 930011238 A KR930011238 A KR 930011238A
Authority
KR
South Korea
Prior art keywords
memory cell
word
gate
static ram
inverter
Prior art date
Application number
KR1019920020846A
Other languages
Korean (ko)
Inventor
이하찌 나이끼
Original Assignee
오리 노리오
소니 가부시기가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP3323795A external-priority patent/JPH05136372A/en
Priority claimed from JP04788492A external-priority patent/JP3297745B2/en
Application filed by 오리 노리오, 소니 가부시기가이샤 filed Critical 오리 노리오
Publication of KR930011238A publication Critical patent/KR930011238A/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

본원 발명은 워드트랜지스터의 게이트와 드라이버트랜지스터의 게이트와의 배치를 변경함으로써, 워드선을 1개로 하여 메모리셀면적의 축소를 도모하고, SRAM을 고집적화한다.The present invention changes the arrangement of the gates of the word transistors and the gates of the driver transistors, thereby reducing the area of the memory cells with one word line, and increasing the SRAM.

제1, 제2의 인버터(11),(12)로 이루어지는 플립플롭(13)과 워드 트랜지스터(14),(15)에 의해 구성한 SARM의 메모리셀(10)로서, 각 워드 트랜지스터(14),(15)를 1개의 워드선(18)으로 형성하고, 워드선(18)의 한쪽 축에제1의 인버터(11)의 드라이버 트랜지스터(23)의 게이트(27)를 배설하고, 그 다른쪽 측에 제2의 인버티(12)의 드라이버 트랜지스터(24)의 게이트(28)를 배설한다. 상기 메모리셀(10)을 1행에 복수개 배치한 메모리셀행을 복수행 배치한 메모리셀어레이(도시하지 않음)로서, 각 우수행째에 배치한 메모리셀을 각기 수행째에 배치한 메모리셀에 대하여 대략 1/2셀분만큼 동일방향축으로 어긋나게 한 것이다.As the memory cell 10 of the SARM constituted by the flip-flop 13 and the word transistors 14 and 15 including the first and second inverters 11 and 12, the word transistors 14, 15 is formed of one word line 18, the gate 27 of the driver transistor 23 of the first inverter 11 is disposed on one axis of the word line 18, and the other side thereof. The gate 28 of the driver transistor 24 of the second invert 12 is disposed. A memory cell array (not shown) in which a plurality of memory cell rows are arranged in one row, wherein the memory cells 10 are arranged in a plurality of rows. It is offset by the same direction axis by 1/2 cell.

Description

스태틱 알에이엠(RAM)의 메모리셀 및 그 메모리셀어레이Memory cell of static RAM and memory cell array

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 제1의 실시예의 레이아웃도.1 is a layout diagram of a first embodiment.

제2도는 제1의 실시예의 회로구성도.2 is a circuit configuration diagram of the first embodiment.

제3도는 제1의 실시예의 게이트패턴의 레이아웃도.3 is a layout diagram of a gate pattern of the first embodiment;

제4도는 제2의 실시예의 레이아웃도.4 is a layout diagram of a second embodiment.

제5도는 제4도중의 A-A선 단면도.5 is a cross-sectional view taken along the line A-A in FIG.

제6도는 제5도중의 게이트 절연막과 게이트의 제조공정도.6 is a manufacturing process diagram of a gate insulating film and a gate in FIG.

제7도는 제3의 실시예의 개략 레이아웃배선도.7 is a schematic layout wiring diagram of a third embodiment.

Claims (3)

제1의 인버터와 제2의 인터버로 형성한 플립플롭과 당해 플립플롭에 접속되는 2개의 워드트랜지스터로 구성한 스태틱 RAM의 메모리셀로서, 상기 각 워드 트랜지스터의 게이트를 1개의 워드선으로 형성하는 동시에, 상기 워드선의 한쪽 측에 상기 제1의 인버터에 있어서의 드라이버 트랜지스터의 게이트를 배설하고, 상기 워드선의 다른쪽 축에 상기 제2의 인버터에 있어서의 드라이버 트랜지스터의 게이트를 배설한 것을 특징으로 하는 스태틱RAM의 메모리셀.A memory cell of a static RAM composed of a flip-flop formed by a first inverter and a second inverter and two word transistors connected to the flip-flop. The gate of each word transistor is formed by one word line. And a gate of the driver transistor in the first inverter on one side of the word line, and a gate of the driver transistor in the second inverter on the other axis of the word line. Memory cell in RAM. 제1항에 있어서, 상기 제1, 제2의 인버터에 있어서의 각 드라이버 트랜지스터의 게이트영역의 일부를 상기 워드트랜지스터의 비트선축 확산층영역에 오버랩하는 상태로 배설한 것을 특징으로 하는 스태틱 RAM의 메모리셀.2. The memory cell of a static RAM according to claim 1, wherein a part of the gate region of each driver transistor in said first and second inverters is disposed so as to overlap with the bit line axis diffusion layer region of said word transistor. . 상기 청구항1 또는 상기 청구항 2기재의 스태틱 RAM의 메모리셀을 1행에 복수개 배치한 메모리 셀행을 복수행 배설한 메모리셀 어레이로서, 상기 메모리실행 중 우수행째에 배치한 메모리셀을 상기 메모리실행 중 기수행째에 배치한 메모리셀에 대하여 대략 1/2 셀분만큼 동일방향측으로 어굿나게 배치한 것을 특징으로 하는 메모리셀어레이.A memory cell array in which a plurality of memory cell rows in which a plurality of memory cells of the static RAM according to claim 1 or 2 are arranged in one row are arranged. A memory cell array, wherein the memory cells arranged in a row are arranged in the same direction by approximately 1/2 cell. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920020846A 1991-11-12 1992-11-07 Memory cell of static RAM and memory cell array KR930011238A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP3323795A JPH05136372A (en) 1991-11-12 1991-11-12 Memory cell of static ram and its memory cell array
JP91-323795 1991-11-12
JP92-47,884 1992-02-04
JP04788492A JP3297745B2 (en) 1992-02-04 1992-02-04 Bit line pair selection circuit for SRAM memory cell array

Publications (1)

Publication Number Publication Date
KR930011238A true KR930011238A (en) 1993-06-24

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Application Number Title Priority Date Filing Date
KR1019920020846A KR930011238A (en) 1991-11-12 1992-11-07 Memory cell of static RAM and memory cell array

Country Status (2)

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US (2) US5422840A (en)
KR (1) KR930011238A (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CZ283018B6 (en) * 1991-02-01 1997-12-17 Merck Sharp And Dohme Limited Imidazole, triazole and tetrazole derivatives, process of their preparation, their use and pharmaceuticals based thereon
JP3824343B2 (en) * 1996-03-29 2006-09-20 富士通株式会社 Semiconductor device
JPH1154632A (en) * 1997-08-01 1999-02-26 Mitsubishi Electric Corp Memory cell layout pattern
JP4214428B2 (en) * 1998-07-17 2009-01-28 ソニー株式会社 Semiconductor memory device
JP3852729B2 (en) * 1998-10-27 2006-12-06 富士通株式会社 Semiconductor memory device
JP3821621B2 (en) * 1999-11-09 2006-09-13 株式会社東芝 Semiconductor integrated circuit
US7158402B2 (en) * 2003-08-06 2007-01-02 Texas Instruments Incorporated Asymmetric static random access memory device having reduced bit line leakage
JP2007013011A (en) * 2005-07-01 2007-01-18 Seiko Epson Corp Ferroelectric memory device and display driving IC
MX2010009775A (en) * 2009-09-08 2011-06-15 Basf Se Method for minimizing emissions while forming a polyurethane foam.

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US4175290A (en) * 1977-07-28 1979-11-20 Hughes Aircraft Company Integrated semiconductor memory array having improved logic latch circuitry
US4158239A (en) * 1977-12-20 1979-06-12 International Business Machines Corporation Resistive gate FET flip-flop storage cell
JPS60134461A (en) * 1983-12-23 1985-07-17 Hitachi Ltd semiconductor storage device
KR940002772B1 (en) * 1984-08-31 1994-04-02 가부시기가이샤 히다찌세이사꾸쇼 Semiconductor integrated circuit and its manufacturing method
US5132771A (en) * 1985-12-27 1992-07-21 Hitachi, Ltd. Semiconductor memory device having flip-flop circuits

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US5446699A (en) 1995-08-29
US5422840A (en) 1995-06-06

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