KR930011106B1 - Word Line Decoder in Semiconductor Memory Devices - Google Patents

Abstract

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Description

Word Line Decoder in Semiconductor Memory Devices

1A is a plan view of a NAND type mask ROM.

FIG. 1B is an equivalent circuit diagram of FIG. 1A. FIG.

1c is an operating state according to FIG.

2 is a block diagram showing a word line selection process according to the present invention.

3 is a detailed circuit diagram of FIG.

Figure 4a is an embodiment of an S predecoder according to the present invention.

Figure 4b is an embodiment of the SS predecoder according to the present invention.

5 is an operation timing diagram of FIG.

* Explanation of symbols for main parts of the drawings

11 bit line aluminum 21 diffusion region

31 polysilicon layer 41 contact hole

51 ion implantation region 100 memory cell arrays

200: column address decoders 300: Y gates

400: word line decoders 500: predecoder

600: row address decoder 30, 50, 70, 90: NOR gates

10, ND41-ND4n, ND51-ND54: NAND gates

11, 13, I4l1-I4n1, I4l2-I4n2, I511-I541, I512-I542: Inverters

SSL1, SSL4: String Selection Lines

ST11, ST42: String Select Transistors

MC111, MC12nm: memory cells WL1, WL2n: word lines

PT1, PTn: pass transistors

PCT1, PCTn: precharge transistors

S1, Sn: S predecoded signals SS1, SS4: SS predecoded signals

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a wordline decoder of a read only memory (ROM) device, and more particularly to a wordline decoder of a highly integrated NAND mask ROM.

The mask ROM refers to a memory device which bakes and fixes memory information using photolithography technology during LSI (large scale integrated circuit) process. Since the mask ROM has a simple circuit configuration and does not require a special manufacturing process, it is excellent in process economical efficiency and is suitable for large capacity among memory devices. Representative methods include a contact mask method, a diffusion layer mask method, and a NAND type method. Etc. In a mask ROM memory cell, the time from the manufacturer to the end user (TAT) must be taken into account, since the mask ROM is semi-custom. For example, the contact mask method of the mask ROMs has a short TAT because the code forming process is close to the final process, while the TAT is long because the diffusion layer mask method is close to the initial process. In the method of storing information, the contact mask method corresponds to the presence or absence of a contact hole, and the diffusion layer mask method corresponds to data # 1 'and' 0 ', respectively, with or without the formation of a transistor in the cell region. On the other hand, the NAND type is designed in such a way that the cell area is minimized and the TAT is not too long. The memory cell transistors are connected in series.

The mask ROM of the NAND type has a polysilicon layer which becomes a diffusion region 21, string select lines SSL1, SSL2 and word lines WL1-WLn, as shown in plan view in FIG. 31, a bit line aluminum layer 11, a contact hole 41 and an ion implantation region 51. As shown in FIG. The transistors in the cell portion of the ion implantation region 51 are depleted, and the other portions are fragmented transistors corresponding to the information # 1 and # 0, respectively. Therefore, it can be seen that the NAND type mask ROM can store information with or without ion implantation.

FIG. 1B is an equivalent circuit diagram of FIG. 1A, which arbitrarily shows only two memory strings.

FIG. 1C shows an operating state of the NAND mask ROM of FIG. 1B.

As shown in FIG. 1B, the basic structure of the NAND type mask ROM includes two string select transistors STi1 and ST (i + 1) 1 and a predetermined number of unit memory cells between the bit line BLi and the ground line GLi. Corresponding field effect transistors MCi1-MCo1 are connected in series to form one unit memory string MSi1, and the gates of the transistors constitute another memory string MSi2 (STi2, ST (i +). 1) 2 and the same rows as the gates of MCi2-mCo2 are commonly connected to each other.

String select lines SSLi and SSLi + 1 are connected to gates of the string select transistors STi1 and Sti2 and ST (i + 1) and ST (i + 1) 2, respectively. Word lines WLi-Wo are connected to gates of + MCo2. In the entire memory cell array, the structures of FIG. 1b are arranged. In FIG. 1B, the depletion transistors STi2, ST (i + 1) 1 and MC (i + 1) 1 correspond to the ion implantation regions 51, 52, and 53 of FIG. 1a, respectively.

The basic operation of the NAND type mask ROM of FIG. 1B will be described with reference to Table 1 below. In order to read the information stored in each memory cell, when the bit line BLi is selected, a read voltage of 1-2V is applied to the bit line BLi. The VCC or OV is applied to the string select lines SSLi and SSLi + 1 to select the memory strings MSi1 and MSi2. For example, when the memory string MSi1 is selected, SSLi must be VCC and SSLi + 1 to be OV. If the memory string MSi2 is selected, SSLi should be OV and SSLi + 1 should be VCC. OV is applied to the selected word line, and VCC is applied to the unselected word line, because the drain-source voltage of the selected memory cell must be sensed on the bit line in order to read information stored in the selected memory cell. to be.

As an example of the above operation, when the memory cell MC (ci + 1) 1 (depletion type) is selected as shown in Table 1, since the transistors in the memory string MSi1 are all conducted, the voltage applied to the bit line BLi is connected to the ground line GLi. Is discharged to sense the data # 1 ', and when the memory cell MC (o-1) 2 is selected, the voltage on the bit line BLi goes to the ground line GLi due to the off state of the memory cell MC (o-1) 2. Since it is not discharged, data # 0 is detected. In the NAND mask ROM cell as described above, the word line is selected by a word line decoder composed of simple logic gates for the signal from the low address decoder. In this conventional method, the mask ROM is miniaturized due to the large capacity and low cost. This requires a large layout area on the substrate. In addition, the increase of the area is accompanied by the length of the line, the delay time of the word line is long, which is a major obstacle to the high-speed read operation.

Accordingly, an object of the present invention is to provide a word line decoder circuit that can be laid out in a small area in accordance with the increase in size and size of a NAND type mask ROM cell array.

It is another object of the present invention to provide a word line decoder circuit capable of appropriate word line selection operation by minimizing time delay of a word line.

In order to achieve the above object, the word line decoder of the present invention detects changes in external input address signals and generates address input means for generating a predetermined signal for selecting a memory string and a word line, and a predetermined output signal of the address input means. Memory string selecting means for selecting the memory string by inputting a predetermined signal pre-decoded externally, and a word for selecting the word line by inputting a predetermined output signal of the address input means and a predetermined signal pre-decoded externally Characterized in that the line selection means.

In order to achieve another object of the present invention, the present invention is characterized by including precharge transistors capable of precharging a power supply voltage level on each of the word lines.

Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

2 is a block diagram of a mask ROM in which the word line decoder of the present invention is incorporated. 2 illustrates a memory cell 100, a column address decoder 200 receiving an external input address signal, a Y gating unit 300, and a word line decoder 400 located outside the memory cell array 100. ), A low address decoder 600 receiving an external input address signal, and a predecoder 500 for inputting the output of the low address decoder 600 to output a predecoded signal to the word line decoder 400. Is shown.

3 illustrates an internal circuit of the word line decoder 400 of FIG. 2 and a memory cell array 100 connected thereto. The memory cell array 100 includes n series transistors MC111, MC121,..., MC1 (n-1), MC1n1 corresponding to unit cells as shown in FIG. ) Are connected in series with two string select transistors ST111 and ST121 to form a memory string, a bit line is connected to the drain or source of the string select transistor ST111, and a ground line is connected to the source or drain of the memory cell MC1n1 at the bottom. GL1 is connected. The unit memory string is symmetric about each of the bit lines BL1-BLm arranged in a row direction, and is also symmetrical around each of the ground lines GL1-GLm and has an iterative structure. It constitutes 100.

At this time, the string select transistors of the memory strings correspond to bit lines, and if one side is a depletion type, the other is a segment type. Therefore, four memory strings are connected to one bit line in the memory cell array 100.

Meanwhile, in FIG. 3, it can be seen that the relationship between the memory strings and the word line decoder corresponds to four memory strings selected by one bit line. The word line decoder 400 inputs a predetermined output of the low address decoder 600, decodes it, and adjusts a signal level and outputs the address input means 411, and outputs the output of the address input means 411. Memory string selecting means 422 and 423 for branching and inputting predetermined predecoding signals SS1-SS4, and predetermined outputs of the address input means 411 and receiving predetermined predecoding signals, respectively. And word line selecting means 433 for inputting (S1-Sn) to substantially select the word line of the memory string. The NAND type logic gate 10 which outputs a high voltage signal even if only one of the address signals Ai, Aj, and Ak output from the row address decoder 600 of FIG. 2 changes. And inverters 11 and 13 for delaying or buffering the output of the logic gate 10.

The memory string selecting means 422 inputs a signal SS1, which is one of an output signal of the address input means 411 and externally decoded signals SS1-SS4, so that at least one of the two inputs is “high”. Level NOR logic gate 30 which outputs the low level to the gate of the string select transistor ST111, and the output signal of the address input means 411 and the external pre-decoding signal SS2 at the level. Is a NOR logic gate 50 which outputs the low to the gate of the string select transistor ST121 when the high level is. In addition, the memory string selecting means 423 inputs the output of the address input means 411 in common and inputs the external predecoding signals SS3 and SS4, respectively, so that at least one of the two inputs is “high”. Is composed of two NOR logic gates 70 and 90 for outputting the low-state signal to the gates of the string select transistors ST131 and ST141, respectively. The word line selecting means 433 has gates simultaneously receiving the output signal of the inverter 11 of the address input means 411, and each of the channel paths is common to the external predecoding signals S1-Sn. Connected word lines WL1 / WL2n, WL2 / WL2n-1, WL3 / WL2n-3… WLn-1 / WLn + 2, WLn / WLn + 1 Fast transistors PT1-PTn connected between common connection points And depleted precharge transistors having drains or sources connected to a power supply voltage, and gates and sources or drains commonly connected on word line connection lines of the fast transistors PT1 -PTn. PCT1-PCTn).

Note that in the configuration of the word line decoder 400, word lines WL1 and WL2n in which 2n word lines WL1-WL2n that span two memory strings arranged in the column direction are located on top of each memory string. ) Are symmetrically connected to two word lines from the word lines WLn and WLn + 1 at the bottom of each memory string, and the n connected lines are the n fast transistors PT1 -PTn. Is connected to the channel channel of).

Two types of predecoding signals are shown in FIG. 3, which are signals output from the predecoder 500 of FIG. 2, and SS1-SS4 is four memory strings MS11, MS12, MS21, and MS22. S1-Sn are used to select two commonly connected word lines WL1 / WL2n, WL2 / WL2n-1, ..., WLn / WLn + 1, respectively. An internal configuration of the predecoder 500 for outputting the predecoding signals SS1-SS4 and S1-S4 is illustrated in FIGS. 4A and 4B.

FIG. 4A is a second pre-decoder (or second decoding means) 520 circuit for outputting pre-decoded signals S1-Sn, wherein the predetermined number of address signals Af-Ah having respective inverted signals are shown in FIG. Inverters I411 in which data lines are arranged, and n NAND gates ND41-ND4n for inputting a predetermined number of the address signals Af, Af, ..., Ah, Ah are respectively connected in series. -I4n1 and I412-I4n2) are connected in series and one NAND gate and two inverters output only one signal. If the number n of memory cells in the unit memory string is 8, the number of inputs of the NAND gates ND41-4D4n will be three. That is, since the number of S signals is eight, three (M = 3) are required by log ₂ 8 = M.

4B illustrates a first predecoder circuit (or first decoding means) 510 for outputting SS signals SS1-SS4 for selecting the four memory strings MS11-MS22. ND51-ND54 and four inverters I511-I541 and I512-I542 are configured as shown in FIG. 4A and decode address signals At and Au having respective inverted signals to output four SS signals. The address signals Af (Af), ..., Ah (Ah), At (At), Au (Au) are all signals from an input address buffer (not shown).

FIG. 5 is a timing diagram illustrating an operation of selecting a word line for selecting memory string MS11 in the circuit of FIG. 3. In FIG. 5, reference numeral 1 denotes a logic gate 10 of the address input means 411. Referring to FIG. Input address signals Ai, Aj, Ah, which are input to the input signal, are denoted by (2), the voltage level of the output node 15 of the inverter 11, and (3) the output node 17 of the inverter 13. Is the predecoding signal SS1 for selecting memory string MS11, (5) the remaining SS predecoding signals SS2, SS3, SS4, and (6) the spring select lines. Voltage level on (SSL2, SSL3, SSL4), (7) selects the voltage level on the string select line SSL1 to select memory strings MS11 or MS12, and (8) selects the pair of word lines (WL1 / WL2n). The voltage level of the S precoding signal S1, 9 is the state of the remaining S precoding signals S2-Sn, and 10 is the selected word. Voltage levels on the lines WL1 / WL2n and 11 denote voltage levels on the remaining word lines WL2-WLn and WLn + 1-WL2n-1, respectively. Reference numerals 51-57 in the timing diagram indicate the signals 1,... … Reference will be made to the operation description of the present invention which shows the operation correlation of (11) below.

Hereinafter, the operation of the present invention will be described in detail with reference to FIGS. 2 to 5. Prior to the description, the circuit diagram of FIG. 3 is a basic configuration for word line selection. In this configuration, the number of word line decoders (hereinafter referred to as P) and the number of word lines (hereinafter referred to as q) and the number of serially connected memory cells (hereinafter n) ) And the number of string selection lines (hereinafter referred to as 1). That is, as can be seen in the configuration of FIG. 3, if n = 8, p corresponds to 1, q = 16, and 1 = 4. This can be established by the following equation (1).

Next, the operation of the word line decoder of FIG. 3 will be described in comparison with the timing diagram of FIG. The following description relates to selecting word line WL1 in memory string MS11.

In order to select the word line WL1, only the selected word line should be grounded as described in the NAND mask RO operation of FIG. 1B, and a predetermined voltage is applied to the selected bit line BL1. First, when all of the predetermined input address signals Ai, Aj, Ah, which are input to the NAND type logic gate (hereinafter referred to as NAND gate) 10 of the address input means 411 are in a high state, The output is in a low state, which causes the potentials of nodes 15 and 17 to be in high and low states, respectively (51).

The signal of the node 51 in the 'high' state is applied to the gates of the fast transistors PT1 -PTn of the word line selecting means 433 to turn on the fast transistors PT1 -PTn. In addition, the signal of the node 17 in the blown state is applied as one input to each of the NOR logic gates 30, 50, 70 and 90 in the memory string selector 422. As assumed herein, in order to select the word line WL1 of the memory string MS11, SS1 of the SS predecoding signals SS1-SS4 is low and S1 of the S predecoding signals S1-Sn is low. Should be The outputs of the SS pre-decode signal SS1 and the S-predecode signal S1 are generated by the decoding operation of the predecoder circuits of FIGS. 4A and 4B, respectively.

Accordingly, the fast transistor PT1 transmits the S1 signal in the low state to the word lines WL1 and WL2n (52), and the NOR gate 30 is connected to the signal of the node 17 in the low state. The string select line SSL1 is made high by inputting the SS1 signal in the low state to output the high state signal (53) (54).

That is, since only the string select transistor ST111 is turned on in the bit line BL1 due to the " high state " of the string select line SSL1, the memory string MS11 is selected. On the other hand, since all of the SS predecoding signals SS2, SS3, and SS4 except for SS1 are in a high state, the remaining NOR gates 50, 70, and 90 except for the NOR gate 30 of the memory string selecting unit 422 are used. ), The potential of the string select lines SSL2, SSL3, and SSL4 is all in the low state because the output of the low frequency is low (55).

In addition, since all of the S predecoding signals S2-Sn except for S1 are in a high state, the memory cells MC121 to MC1n1 other than the memory cells MC111 having a gate connected to the word line WL1 are in the on state. ).

Therefore, since the information of the selected memory cell MC111 of the selected memory string MS11 appears on the bit line BL1, a read operation is performed. In the circuit of FIG. 3, gates and source or drain terminals are connected on respective lines between the fast transistors PT1 -PTn and the word lines WL1 -WL2n, and a power supply voltage VCC is connected to each drain or source terminal. The precharge transistors PCT1-PCTn connected to the first precharge transistors PCT1-PCTn maintain the VCC level before the unselected S predecoding signal goes to the high level to speed up the word line selection operation. For example, when the word line WL2 is selected after the word line WL1 is selected, the S pre decoding signal S1 is in a high state and the S pre decoding signal S2 is in a low state. At this time, if the rising to the high level of S1 is delayed, the selection operation of the word line WL2 is naturally delayed and an error may occur in operation.

However, the precharge transistor PCT1 connected on the line 1 has the VCC level before the S1 signal, which is in a high state due to a previous low state, passes through the line 1. Since the above problems can be prevented.

Those skilled in the art will readily understand that the presence of the precharge transistors PCT1-PCTn can speed up the read operation as well as the word line selection operation.

In the above-described embodiment of the present invention, a structure in which only two word lines are bundled, but other methods, such as a method of tying a plurality of word lines within a range where there is no problem in the size and operation of the entire memory device, may be possible. In the above embodiment, a depletion-type NMOS field effect transistor is used as the precharge transistor, but other constituent means and elements capable of the same operation as the transistor are also possible. In addition, in the above embodiment, the NMOS field effect transistor is used as the pass transistor, but other constituent means and elements capable of the same operation and effect as the transistor may be possible.

As described above, the present invention binds word lines to a plurality of memory strings and receives a pre-decoded signal from the outside to decode word lines, thereby reducing layout limitations due to miniaturization of memory cells and reducing the size of the entire chip. There is an advantage. In addition, the present invention has the effect of enabling a high speed read operation by enabling precharging to a power supply voltage VCC level even in a small transistor using a depletion transistor operating in a saturation region.

Claims (20)

A semiconductor memory device comprising one bit line and a predetermined number of word lines, a plurality of memory strings each consisting of NAND memory cells selected by the bit lines and word lines, and word line decoders. And the word line decoders are respectively connected to a plurality of word lines in different memory strings so that any word line decoder can select the plurality of word lines. 2. The semiconductor memory device according to claim 1, wherein a plurality of word lines selected by the word line decoder are connected to memory cells at equal positions from the bit lines among the plurality of memory strings. In a semiconductor memory device including a low address decoder 600, a column address decoder 200, and a memory cell array 100, a word line decoder 400 receives predetermined external address signals from the low address decoder 600. Address input means 411 for inputting and outputting predetermined signals for selecting a memory string and a word line, and first decoding means 510 for outputting signals for selecting the memory string by predecoding predetermined external address signals. Second decoding means 520 for pre-decoding predetermined external address signals and outputting signals for selecting word lines, and a predetermined output signal of the address input means 411 and the first decoding means 510. Memory string selecting means 422 for outputting a signal for selecting a memory string by inputting output signals of A plurality of word lines in different memory strings comprising word line selecting means 433 for inputting a predetermined output signal of the input means 411 and output signals of the second decoding means to output a signal for selecting a word line. The semiconductor memory device, characterized in that can be selected. 4. The semiconductor memory device according to claim 3, wherein said address input means (411) has two output signals inverted from each other. 4. The semiconductor memory device according to claim 3, wherein the address input means (411) can output a signal capable of detecting a change in external input address signals. 4. The semiconductor memory device according to claim 3, wherein the output signals of the first and second decoding means (520) can be supplied from the outside of the memory chip. 4. The semiconductor memory device according to claim 3, wherein the memory string selecting means (422) selects the memory string according to the states of the output signals of the first decoding means (510). 4. The word line selecting means 433 of claim 3, wherein the word line selecting means 433 is connected to each output signal terminal of the second decoding means 520 and a source or a drain thereof, and gates thereof are predetermined output signal terminals of the address input means 411. Pass transistors connected to the connection points of the word lines having a plurality of drains or sources connected to each other, source or drains connected to a power supply voltage terminal, and gates and drains or sources connected to the connection points of the word lines and the pass transistors. And precharge transistors commonly connected to respective lines of the plurality of lines. 9. The semiconductor memory device according to claim 8, wherein the pass transistors gate the output signals of the second decoding means (520) to word lines. 10. The semiconductor memory device according to claim 9, wherein the pass transistors may be N-type insulated gate field effect transistors. 10. The semiconductor memory device according to claim 8, wherein the threshold voltage of the precharge transistors is equal to or less than OV. 12. The semiconductor memory device according to claim 11, wherein the precharge transistors may be insulated gate field effect transistors operating in a saturation region. A word line decoder of a semiconductor memory device, comprising: address input means for detecting a change in external input address signals to generate predetermined signals for selecting a memory string and a word line, a predetermined output signal of the address input means, and an external free signal; Memory string selecting means for selecting the memory string by inputting a predetermined signal decoded, and word line selecting means for selecting the word line by inputting a predetermined output signal of the address input means and a predetermined signal externally decoded Word line decoder, characterized in that consisting of. The method of claim 13, wherein the word line selecting means is connected to a source or a drain of each of the predetermined signals pre-decoded from the outside, and each of the gates is connected to a predetermined output signal terminal of the address input means and is connected to a drain or source. Pass transistors connected to word lines, and a source or drain connected to a power supply voltage terminal, and gates and drains or sources connected to each other between the word lines and the fast transistors. A word line decoder comprising charge transistors. 15. The wordline decoder of claim 14, wherein the pass transistors gate the externally predecoded signals to the wordlines. 16. The word line decoder of claim 15, wherein the pass transistors may be N-type insulated gate field effect transistors. 15. The word line decoder of claim 14, wherein the threshold voltage of the precharge transistors is equal to or less than OV. 18. The word line decoder of claim 17, wherein the precharge transistors may be insulated gate field effect transistors operating in a saturation region. A semiconductor memory device having one bit line, a predetermined number of word lines, and a plurality of memory strings each consisting of NAND type memory cells selected by the bit lines and word lines, wherein: A word line decoder connected to a plurality of word lines in different memory strings so that any word line decoder selects a plurality of word lines, and a precharge for precharging a power supply voltage level to each of the word lines; A semiconductor memory device comprising a charge transistor. 20. The semiconductor memory device according to claim 19, wherein the precharge transistor comprises a depletion transistor in which a gate is connected to the word line and a channel is formed between the word line and a power supply voltage terminal.

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