KR930011054B1 - 상이한 층 레벨에 위치한 배선층간의 전기 접촉을 형성하는 방법 - Google Patents
상이한 층 레벨에 위치한 배선층간의 전기 접촉을 형성하는 방법 Download PDFInfo
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- KR930011054B1 KR930011054B1 KR1019900008356A KR900008356A KR930011054B1 KR 930011054 B1 KR930011054 B1 KR 930011054B1 KR 1019900008356 A KR1019900008356 A KR 1019900008356A KR 900008356 A KR900008356 A KR 900008356A KR 930011054 B1 KR930011054 B1 KR 930011054B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76862—Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76844—Bottomless liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (16)
- a) 반도체 기판(1)위의 절연막(2)위에 제1도체 배선층(3)을 형성하는 단계. b) 상기 제1도체 배선층과 상기 절연막 위에 층간 절연막(4)을 형성하는 단계. c) 상기 층간 절연막의 접촉홀(6), 상기 접촉홀을 통하여 노출되는 상제 제1도체 배선층의 표면부를 형성하는 단계를 포함하는 상이한 층 레벨에 위치한 배선층간의 전기접촉을 형성하는 방법에 있어서, 상기 방법은 d) 제1도체 배선층의 상기 표면부와 상기 층간 절연막 위에 금속중간층(8)을 형성하는 단계. e) 상기 접촉홀을 통하여 노출된 상기 금속 중간층의 일부와 제1도체 배선층의 상기 표면부위에 형성된 산화막(7)을 에칭과정에 의하여 소거되는 단계. f) 상기 제1과 제2도체 배선층사이에 전기접촉이 형성되도록 상기 접촉홀안과 상기 층간 절연막위에 제2도체 배선층(9)을 형성하는 단계로 구비되며, 상기 단계((a) 내지 (f))은 순서대로 실행되며 상기 단계((a) 내지 (f))는 진공중에서 연속적으로 실행되는 것을 특징으로 하는 상이한 층레벨에 위치한 배선층간의 전기접촉을 형성하는 방법.
- 제1항에 있어서, 상기 금속 중간층(8)은 산소와 용이하게 결합하는 금속물질로 구성되는 것을 특징으로 하는 방법.
- 제1항에 있어서, 상기 금속 중간층(8)은 티탄늄으로 구성되는 것을 특징으로 하는 방법.
- 제1항에 있어서, 상기 금속 중간층(8)은 알루미늄으로 구성되는 것을 특징으로 하는 방법.
- 제1항에 있어서, 상기 금속 중간층(8)은 티탄늄과 알루미늄의 합금으로 구성되어있는 것을 특징으로 하는 방법.
- 제1항 내지 제5항중 어느 한 항에 있어서, 상기 단계(d)는 스퍼터링 과정에 의하여 상기 금속 중간층(8)을 형성하는 단계로 구성되는 것을 특징으로 하는 방법.
- 제1항 내지 제5항중 어느 한 항에 있어서, 상기 단계(d)는 진공증착 과정에 의하여 상기 금속 중간층(8)을 형성하는 단계로 구성되는 것을 특징으로 하는 방법.
- 제1항 내지 제5항중 어느 한 항에 있어서, 상기 단계(e)에 이용된 상기 에칭과정은 스퍼터 에칭과정인 것을 특징으로 하는 방법.
- 제1항 내지 제5항중 어느 한 항에 있어서, 상기 단계(e)가 실행되기전에 상기 반도체 기판(1)을 가열하는 단계를 더 포함하는 것을 특징으로 하는 방법.
- 제8항에 있어서, 상기 스퍼터에칭은 아르곤 이온을 일정하게 나가게 하는 전계가 상기 반도체 기판(1)에 인가된 상태에서 상기 금속 중간층(8)에 상기 아르곤이온을 투사하여 실행되는 것을 특징으로 하는 방법.
- 제1항 내지 제5항중 어느 한 항에 있어서, 상기 전계는 상기 반도체 기판(1)에 수직방향인 것을 특징으로 하는 방법.
- 제1항 내지 제5항중 어느 한 항에 있어서, 상기 제1 및 제2도체 배선층(3,9) 각각은 순수한 알루미늄으로 구성되는 것을 특징으로 하는 방법.
- 제1항 내지 제5항중 어느 한 항에 있어서, 상기 제1 및 제2도체 배선층(3,9) 각각은 알루미늄과 실리콘으로 구성되어 있는 것을 특징으로 하는 방법.
- 제1항 내지 제5항중 어느 한 항에 있어서, 상기 제1 및 제2도체 배선층은 알루미늄과 구리로 구성되어 있는 것을 특징으로 하는 방법.
- 제1항 내지 제5항중 어느 한 항에 있어서, 제1 및 제2도체 배선층은 각각은 알루미늄, 티탄늄 및 구리로 구성되어 있는 것을 특징으로 하는 방법.
- 제1항 내지 제5항중 어느 한 항에 있어서, 제1 및 제2도체 배선층 각각은 알루미늄, 티탄늄 및 실리콘으로 구성되어 있는 것을 특징으로 하는 방법.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1143395A JPH038359A (ja) | 1989-06-06 | 1989-06-06 | 半導体装置の製造方法 |
JP1-143395 | 1989-06-06 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910001923A KR910001923A (ko) | 1991-01-31 |
KR930011054B1 true KR930011054B1 (ko) | 1993-11-20 |
Family
ID=15337768
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900008356A KR930011054B1 (ko) | 1989-06-06 | 1990-06-07 | 상이한 층 레벨에 위치한 배선층간의 전기 접촉을 형성하는 방법 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5081064A (ko) |
EP (1) | EP0401688B1 (ko) |
JP (1) | JPH038359A (ko) |
KR (1) | KR930011054B1 (ko) |
DE (1) | DE69025801T2 (ko) |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5177589A (en) * | 1990-01-29 | 1993-01-05 | Hitachi, Ltd. | Refractory metal thin film having a particular step coverage factor and ratio of surface roughness |
JPH088301B2 (ja) * | 1990-06-07 | 1996-01-29 | 株式会社東芝 | 半導体装置の製造方法 |
JP2598335B2 (ja) * | 1990-08-28 | 1997-04-09 | 三菱電機株式会社 | 半導体集積回路装置の配線接続構造およびその製造方法 |
JPH04242088A (ja) * | 1991-01-16 | 1992-08-28 | Nec Corp | Icソケット |
JPH06177127A (ja) * | 1991-05-30 | 1994-06-24 | Sony Corp | 配線形成方法 |
JP3139781B2 (ja) * | 1991-08-07 | 2001-03-05 | 沖電気工業株式会社 | 半導体装置およびその製造方法 |
US5200359A (en) * | 1991-10-03 | 1993-04-06 | Micron Technology, Inc. | Method of decreasing contact resistance between a lower elevation aluminum layer and a higher elevation electrically conductive layer |
US5376820A (en) * | 1992-02-05 | 1994-12-27 | Ncr Corporation | Semiconductor fuse structure |
JP2755035B2 (ja) * | 1992-03-28 | 1998-05-20 | ヤマハ株式会社 | 多層配線形成法 |
JPH065715A (ja) * | 1992-06-18 | 1994-01-14 | Sony Corp | 配線層の形成方法 |
US5486492A (en) * | 1992-10-30 | 1996-01-23 | Kawasaki Steel Corporation | Method of forming multilayered wiring structure in semiconductor device |
JPH07105441B2 (ja) * | 1992-11-30 | 1995-11-13 | 日本電気株式会社 | 半導体装置の製造方法 |
US5443995A (en) * | 1993-09-17 | 1995-08-22 | Applied Materials, Inc. | Method for metallizing a semiconductor wafer |
US5747360A (en) * | 1993-09-17 | 1998-05-05 | Applied Materials, Inc. | Method of metalizing a semiconductor wafer |
US6726776B1 (en) | 1995-11-21 | 2004-04-27 | Applied Materials, Inc. | Low temperature integrated metallization process and apparatus |
US5877087A (en) | 1995-11-21 | 1999-03-02 | Applied Materials, Inc. | Low temperature integrated metallization process and apparatus |
US6077781A (en) | 1995-11-21 | 2000-06-20 | Applied Materials, Inc. | Single step process for blanket-selective CVD aluminum deposition |
US6016012A (en) * | 1996-11-05 | 2000-01-18 | Cypress Semiconductor Corporation | Thin liner layer providing reduced via resistance |
US6110828A (en) * | 1996-12-30 | 2000-08-29 | Applied Materials, Inc. | In-situ capped aluminum plug (CAP) process using selective CVD AL for integrated plug/interconnect metallization |
US6537905B1 (en) * | 1996-12-30 | 2003-03-25 | Applied Materials, Inc. | Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug |
US6139697A (en) * | 1997-01-31 | 2000-10-31 | Applied Materials, Inc. | Low temperature integrated via and trench fill process and apparatus |
US5930669A (en) | 1997-04-03 | 1999-07-27 | International Business Machines Corporation | Continuous highly conductive metal wiring structures and method for fabricating the same |
US5985762A (en) * | 1997-05-19 | 1999-11-16 | International Business Machines Corporation | Method of forming a self-aligned copper diffusion barrier in vias |
US5989623A (en) * | 1997-08-19 | 1999-11-23 | Applied Materials, Inc. | Dual damascene metallization |
US6228754B1 (en) * | 1999-01-05 | 2001-05-08 | Advanced Micro Devices, Inc. | Method for forming semiconductor seed layers by inert gas sputter etching |
US6207558B1 (en) * | 1999-10-21 | 2001-03-27 | Applied Materials, Inc. | Barrier applications for aluminum planarization |
EP1442153A4 (en) * | 2001-10-11 | 2007-05-02 | Epion Corp | GCIB PROCESSING FOR IMPROVEMENT OF CONNECTING CONTACTS AND IMPROVED CONNECTION CONTACT |
JP4774931B2 (ja) * | 2005-11-07 | 2011-09-21 | コニカミノルタビジネステクノロジーズ株式会社 | 現像装置、プロセスカートリッジ及び画像形成装置 |
KR100938347B1 (ko) * | 2007-05-18 | 2010-01-22 | 김재화 | 분말화된 음식물 쓰레기 소각 장치 |
US10679891B2 (en) * | 2017-06-30 | 2020-06-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming interconnect structures using a vacuum environment |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4107726A (en) * | 1977-01-03 | 1978-08-15 | Raytheon Company | Multilayer interconnected structure for semiconductor integrated circuit |
US4507852A (en) * | 1983-09-12 | 1985-04-02 | Rockwell International Corporation | Method for making a reliable ohmic contact between two layers of integrated circuit metallizations |
DE3683679D1 (de) * | 1985-04-26 | 1992-03-12 | Fujitsu Ltd | Verfahren zur herstellung einer kontaktanordnung fuer eine halbleiteranordnung. |
JPH0719841B2 (ja) * | 1987-10-02 | 1995-03-06 | 株式会社東芝 | 半導体装置 |
US4962414A (en) * | 1988-02-11 | 1990-10-09 | Sgs-Thomson Microelectronics, Inc. | Method for forming a contact VIA |
US4998157A (en) * | 1988-08-06 | 1991-03-05 | Seiko Epson Corporation | Ohmic contact to silicon substrate |
US4983543A (en) * | 1988-09-07 | 1991-01-08 | Fujitsu Limited | Method of manufacturing a semiconductor integrated circuit having an interconnection wire embedded in a protective layer covering the semiconductor integrated circuit |
-
1989
- 1989-06-06 JP JP1143395A patent/JPH038359A/ja active Pending
-
1990
- 1990-05-31 DE DE69025801T patent/DE69025801T2/de not_active Expired - Fee Related
- 1990-05-31 EP EP90110375A patent/EP0401688B1/en not_active Expired - Lifetime
- 1990-06-04 US US07/532,709 patent/US5081064A/en not_active Expired - Fee Related
- 1990-06-07 KR KR1019900008356A patent/KR930011054B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JPH038359A (ja) | 1991-01-16 |
US5081064A (en) | 1992-01-14 |
EP0401688B1 (en) | 1996-03-13 |
DE69025801T2 (de) | 1996-07-25 |
DE69025801D1 (de) | 1996-04-18 |
KR910001923A (ko) | 1991-01-31 |
EP0401688A2 (en) | 1990-12-12 |
EP0401688A3 (en) | 1991-07-31 |
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Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19900607 |
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