KR930008431B1 - Digital PLL State Detection Circuit - Google Patents

Abstract

No content.

Description

Digital PLL State Detection Circuit

1 is a conventional PLL state detection circuit.

2 is a schematic diagram of the present invention.

3 shows a concrete circuit according to FIG. 2.

* Explanation of symbols for main parts of the drawings

401: phase comparison unit 402: bypass unit

403: peak detection unit 404: switching and indicating unit

The present invention relates to a phase locked loop (PLL) state detection circuit, and more particularly to a PLL state detection circuit for detecting a state in which a loop is locked or not locked in a digital phase locked loop (PLL). It is about.

In general, a conventional PLL state detection circuit includes a voltage comparator composed of two operational amplifiers, and compares a voltage between a constant reference voltage and a low pass filter output voltage.

In the case of detecting the PLL state by such a conventional method, it is difficult to set the exact voltage range in which the voltage controlled oscillator is locked, which makes it difficult to detect the PLL state and has disadvantages in terms of mass production.

In addition, the "digital PLL state detection circuit (hereinafter referred to as" prior patent ") of Publication No. 89-4120, filed by the applicant of the present application on June 27, 1987 and filed on October 27, 1989, was filed. 1 is shown.

The prior patent shown in FIG. 1 uses a type of phase / frequency comparator using a D-type flip-flop 21 and a retriggerable one-shot multivibrator 22 to control the PLL state according to the control voltage variation of the voltage controlled oscillator. This circuit prevents erroneous detection.

The preceding patent merely complicates the circuit by using the D-type flip-flop and the retriggerable one-shot multivibrator to detect the lock and unlock state of the PLL as "high" or "low". Accordingly, there was a disadvantage in terms of cost in mass production of the product.

In addition, there is no support function to inform the user of unlocking of the PLL state, and it is troublesome to apply to all digital PLL circuits because the value of the resistor (R21) and the capacitor (C21) must be changed whenever the frequency used in the PLL is changed. There was this.

Accordingly, it is an object of the present invention to provide a digital PLL state detection circuit which can easily constitute a circuit using a general-purpose digital gate element, an analog element, etc. in view of the above problems.

It is another object of the present invention to provide a digital PLL state detection circuit that can be applied to all digital PLL circuits regardless of the frequency range of use.

It is another object of the present invention to provide a digital PLL state detection circuit having excellent price competitiveness in mass production.

It is still another object of the present invention to provide a digital PLL state detection circuit which can be easily used by a user and has excellent reliability.

Hereinafter, the present invention will be described in detail.

2 is a schematic diagram of a digital PLL state detection circuit according to the present invention, which inputs a reference input signal to the input terminal R through the input line S1 and simultaneously inputs a predetermined divided oscillation output signal through the input line S2. A phase detector 11 for inputting the terminal V to detect a phase thereof, and an output of the phase detector 11 to input resistors R11-R17, capacitors C11-C14, and operational amplifiers 12; A low pass filter 100 to be compared with the reference signal, a voltage controlled oscillator 13 connected to the oscillation capacitor C15 by inputting a signal output from the low pass filter 100 to an input terminal Vin, and A division circuit 14 for dividing the oscillation output signal output from the oscillation output terminal fout of the voltage controlled oscillator 13 to an arbitrary value N, and a reference input signal line of the phase detector 11 ( S1) and comparison input signal line (S2) to detect the locked or unlocked state of the PLL A phase comparator 401 and a phase comparator 401 connected to the phase comparator 401 to bypass the output of the phase comparator 401 at the time of locking, and the bypass part. Connected to 402, the output of the phase comparator 401 is connected to the peak detector 403 and the peak detector 403 to unlock the PLL when the unlocked when the PLL is unlocked and the user is switched And a switching and indicating unit 404 for indicating an unlock state.

3 is a detailed circuit diagram of the digital PLL state detector 400 including the phase comparator 401, the bypass 402, the peak detector 403, and the switching and indicating unit 404.

The phase comparator 401 is connected to the input lines S1 and S2 of the phase detector 11 and consists of an exclusive ore gate EOR1 for deriving an exclusive logical sum according to the input. The pass unit 402 is composed of a capacitor C1 that selectively bypasses according to the output of the exclusive oage EOR1, and the peak detector 403 is not bypassed by the capacitor C1. And a diode (D1) and an electrolytic capacitor (C2) for DC-outputting the output of the exclusive oragate (EOR1), and the switching and indicating unit 404 is the diode (D1) and the electrolytic capacitor ( For voltage drop connected between the switching transistor (Q1), the biasing resistors (R1, R2), and the power supply voltage (VCC) switching transistor (Q1) for inputting the output of C2) to alarm the unlock state of the PLL. Resistor (R3) and Marking Feet It consists of a diode (LED1).

An alarm buzzer is used between the collector of the transistor Q1 and the power supply voltage VCC to inform the user of the unlock state of the PLL as an alarm instead of the light emitting diode LED1.

2, the phase comparison unit 401 inputs the output of the comparison input signal line S2 output from the reference input signal line S1 of the phase detector 11 and the output terminal Q of the divider 14, Compare the phases.

Here, the output of the phase comparison unit 401 is locked or unlocked when the PLL including the phase detector 11, the low pass filter 100, the voltage controlled oscillator 13, and the frequency divider circuit 14 is locked. Different outputs.

The bypass unit 402 bypasses the output only when the output of the phase comparator 401 is locked, and passes the output of the phase comparator 401 as it is when unlocked. Let's do it. Accordingly, the peak detector 403 detects the peak of the output of the phase comparator 401 input at the time of unlocking, and converts the peak detector 403 into a DC voltage which is a voltage having a constant magnitude in time. That is, the peak detector 403 converts an irregular AC signal having a DC component into a DC voltage.

The DC voltage output indicating the unlocked state of the peak detector 403 is input to the switching and indicating unit 404.

The switching and indicating unit 404 inputs the output of the peak detector 403 to instruct or alert the user to the unlock state of the PLL. Therefore, when the PLL is unlocked, the user knows that the PLL is unlocked by an instruction or an alarm, thereby facilitating quick countermeasures.

In addition to the above description, the operation of the digital PLL state detection unit 400 shown in FIG. 3 will be described in detail.

The two input signals S1 and S2 of the exclusive oragate EOR1 are the same as the inputs of the phase detector 11 of the PLL. In this case, when the PLL is locked, frequencies input to the exclusive oragate EOR1 are the same and two states are possible. That is, one case is when the signal of the reference input signal line S1 is out of phase with the signal S2, and the other is when the signal of S1 is later than the signal S2. At this time, regardless of the above cases, the output of the exclusive oragate EOR1 has a constant period at the time of locking and a "high" state is output as much as the phase difference between the two inputs.

The output of "high" is a signal having an AC component and is bypassed by the capacitor C1 to maintain the ground level.

Therefore, the switching transistor Q1 operates in a "turn-around" because the voltage input to the base is "low". Therefore, the light emitting diode LED1 also maintains the off state.

However, when the PLL is uncrossed, an AC signal having an irregular period and a DC component is output to an output terminal of the exclusive oragate EOR1.

Since the output of the exclusive oragate EOR1 during the unlocking is a signal having a DC component, the output is input to the anode of the diode D1 without being bypassed by the capacitor C1.

The diode D1 and the electrolytic capacitor C2 detect the peak and convert it to a DC voltage. At this time, a DC voltage of about 1-3V is generated.

The DC voltage is input to the base of the switching transistor Q1 through the resistor R1. Thus, the transistor Q1 is turned on. Therefore, in response to the turn-on operation of the transistor Q1, an operating voltage is applied to the light emitting diode LED1 to emit light. Accordingly, the user can recognize the light emitting operation of the light emitting diode LED1 to know that the current PLL state is unlocked. In this case, an alarm buzzer or the like may be used instead of the light emitting diode LED1 to indicate an unlock state of the PLL.

In this case, when the current flowing into the base of the transistor Q1 is Ib, the current flowing through the collector load is I, and the current amplification factor of the transistor Q1 is hfe, Ib> I> hfe is a saturation condition of the transistor. The bias resistors R1 and R2 are formed.

In the present invention, the switching transistor Q1 is used as the NPN type, but may be replaced with the PNP type and the remaining related elements may be replaced accordingly.

As described above, the present invention can easily detect a PLL state of a device using a digital PLL, and a circuit can be constructed by a gate element and a general analog element, which are general-purpose digital ICs, thereby simplifying hardware and in terms of cost. It is advantageous. In addition, by using a kind of phase comparison method, it is possible to prevent erroneous detection due to control voltage variation of the voltage controlled oscillator, thereby improving the reliability of the product. In addition, the present invention is advantageous in terms of mass production, since the separate operation is omitted unlike the existing circuit during mass production, there is an advantage that does not have a busy effect such as malfunction due to impedance mismatch of the PLL.

Claims (10)

Voltage control for providing a predetermined oscillation output by inputting a phase detector 11, a low pass filter 100 for inputting and comparing respective outputs of the phase detector 11, and an output of the low pass filter 100; In the digital PLL state detection circuit having an oscillator 13 and a division circuit 14 for dividing the oscillation output of the voltage controlled oscillator 13 at a predetermined division ratio, each of the inputs input to the phase detector 11 is provided. A phase comparison means for comparing phases, bypass means for selectively bypassing according to the output of the phase comparison means, and outputs of the phase comparison means not bypassed by the bypass means in a constant time Peak detection means for outputting the signal and indicating means for indicating the locked or unlocked state of the loop corresponding to the output of the peak detection means. Digital PLL state detecting circuit that. 2. The phase comparator according to claim 1, wherein said phase comparing means is connected to input lines (S1, S2) of said phase detector (11) and comprises an exclusive oragate (EOR1) for deriving exclusive logic according to said input. Digital PLL state detection circuit, characterized in that. 2. The digital PLL of claim 1, wherein the bypass means is comprised of a capacitor C1 connected between the output of the phase comparing means and ground to bypass the output of the phase comparing means when the loop is locked. State detection circuit. 2. A diode according to claim 1, wherein the peak detection means comprises a diode (D1) and an anode of the diode (D1) having an anode connected to the output of the phase comparison means to bring the non-passed output of the phase comparison means to a DC voltage. A digital PLL state detection circuit comprising an electrolytic capacitor (C2) connected between grounds. 2. The method of claim 1, wherein the indicating means comprises: bias resistors R1 and R2 connected to an output of the peak detecting means, transistors Q1 connected to a base of the resistor R1, and a collector of the transistor Q1; A digital PLL state detection circuit comprising a resistor (R3) and a light emitting diode (LED1) connected between a power supply voltage (VCC). A digital PLL state detection circuit having a phase detector 11, a low pass filter 100, a voltage controlled oscillator 13, and a divider circuit 14, wherein the reference input signal line S1 of the phase detector 11 is provided. And a phase comparator 401 connected to a comparison input signal line S2 for detecting a locked or unlocked state of the PLL, and a phase comparator 401 connected to the phase comparator 401 when the lock is performed. Bypass unit 402 for bypassing the output of the) and the peak detector 403 connected to the bypass unit 402 to make the output of the phase comparator 401 to the DC voltage when the unlocking; And a switching and indicating unit (404) connected to the peak detection unit (403) to switch when the PLL is unlocked to alert the user to the unlock state. 7. The phase comparator 401 of claim 6, wherein the phase comparator 401 comprises an exclusive ore gate EOR1 for exclusively logically outputting the inputs of the phase detector 11 to the bypass unit 402. Digital PLL state detection circuit. 8. The capacitor of claim 7, wherein the bypass unit 402 is configured to selectively bypass the output of the exclusive oragate EOR1 to output the peak detection unit 403. Digital PLL state detection circuit. The diode D1 and the defining capacitor (D1) for outputting the undetected output of the exclusive oragate (EOR1) to the switching and indicating unit 404 under DC. C2) digital PLL state detection circuit. The switching transistor Q1 and the bias resistor R1 for inputting the outputs of the diode D1 and the electrolytic capacitor C2 to alert the unlock state. R2), an alarm buzzer connected between a power supply voltage VCC and a collector of the transistor Q1.

Images