KR930007080A - π / 4DQPSK digital modulation method and apparatus - Google Patents

Abstract

The present invention relates to a DQPSK (Quad Phase Shift Keying) method and apparatus for transmitting digital signals.

The modulator of the present invention calculates in advance the output waveform of the baseband IQ channel according to the phase shift amount of the output signal corresponding to the change of the input data string, stores the sampled values in the storage means, and reads them out according to the pattern of the input data string. It is implemented by the method.

According to the present invention, the amount of phase shift of the output signal is limited to an integer multiple of π / 4, and in particular, so that no phase shift through zero occurs, so that the linear characteristic of the output amplifier is not more difficult than that of the conventional DQPSK method. In addition, the modulation circuit can be digitalized to simplify the circuit configuration and reduce the power consumption.

Description

π / 4DQPSK digital modulation method and device therefor

Since this is an open matter, no full text was included.

4 is a specific embodiment according to the present invention.

Claims (7)

In the DQPSK modulation method including a baseband filter (30, 40), a 90 ° phase shifter (70), carrier modulators (50, 60), a synthesizer (80), and a bandpass filter (90), the phase shift of the output signal Calculating the output waveform of the baseband IQ channel according to the amount in advance and storing it in the storage means, and designating the upper address of the storage means as a combination of a predetermined number of bits obtained by serial / parallel conversion of a digital signal input by binary code; And a step of sequentially and periodically designating a lower address corresponding to the upper address, and digital / analog conversion of data read out from the storage means. DQPSK modulation. The π / 4-DQPSK modulation method according to claim 1, wherein the phase shift amount of the output signal is limited to an integer multiple of π / 4-DQPSK. The π / -4 modulation method of claim 1, wherein the number of data bits to be serially / parallel converted is determined according to a pulse response characteristic of a baseband filter. The output waveform of the baseband IQ channel according to the phase shift amount of the output signal is determined by superimposing the pulse response characteristics of the baseband filter by predetermined data bits before and after the data bits at any time point. Π / 4-DQPSK modulation scheme. In the DQPSK modulation method including the baseband filters 30 and 40, the 90 ° phase shifter 70, the carrier modulators 50 and 60, the synthesizer 80, and the bandpass filter 90, Storage means (21, 23) for precomputing an output waveform of the baseband IQ channel and storing a predetermined number of sampled values in one bit section; The first address specifying means 10, which provides the means 21 and 23 as an upper address, and the lower address corresponding to the upper address provided by the first address specifying means 10, are sequentially and periodically designated. Digital / analog converting means (22) for digitally / analog converting data read through the second addressing means (100) and the first addressing means (10) and the second addressing means (100). 24) a π / 4-DQPSK modulation circuit. 6. The π / 4-DQPSK modulation circuit according to claim 5, wherein the first addressing means (10) comprises a shift register (11) and a divider (12). 7. The π / 4-DQPSK modulation circuit according to claim 6, characterized in that the division ratio of the divider (12) is determined as a predetermined sampling number in one bit section of the input data string. ※ Note: The disclosure is based on the initial application.