KR930006239Y1 - Barrel elimination circuit for monitor - Google Patents
Barrel elimination circuit for monitor Download PDFInfo
- Publication number
- KR930006239Y1 KR930006239Y1 KR2019880010425U KR880010425U KR930006239Y1 KR 930006239 Y1 KR930006239 Y1 KR 930006239Y1 KR 2019880010425 U KR2019880010425 U KR 2019880010425U KR 880010425 U KR880010425 U KR 880010425U KR 930006239 Y1 KR930006239 Y1 KR 930006239Y1
- Authority
- KR
- South Korea
- Prior art keywords
- monitor
- barrel
- output
- horizontal
- exclusive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000008030 elimination Effects 0.000 title description 3
- 238000003379 elimination reaction Methods 0.000 title description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/391—Resolution modifying circuits, e.g. variable screen formats
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Amplifiers (AREA)
- Details Of Television Scanning (AREA)
Abstract
내용 없음.No content.
Description
제1도는 본 고안에 따른 모니터 배럴 현상 제거 회로도.1 is a monitor barrel development circuit diagram according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 수평 주파수 조절단 20 : 캐스코드증폭 회로10: horizontal frequency control stage 20: cascode amplifier circuit
30 : 수평 출력단 OP1, OP2 : 오피앰프30: horizontal output stage OP1, OP2: op amp
EX1, EX2 : 익스클루시브 오아게이트 Q1, Q2 : 트랜지스터EX1, EX2: Exclusive Oagate Q1, Q2: Transistor
R1∼R8 : 저항R1 to R8: resistance
본 고안은 모니터 회로에 관한 것으로,특히 수평 주파수 조절단의 주파수차이 전압을 수평 출력단에 인가시켜 모니터의 배럴(Barrel : 화면이 상하·좌우로 커지는 것을 말함)현성을 제거시키도록 하는데 적당하도록한 모니터의 배럴 현상 제거 회로에 관한 것이다.The present invention relates to a monitor circuit, and in particular, a monitor adapted to apply a frequency difference voltage of a horizontal frequency adjusting stage to a horizontal output stage so as to remove a barrel of the monitor. Of the barrel phenomenon removal circuit.
종래의 모니터 회로에 있어서는 수평 주파수 조절단의 주파수 차이에 따라 모니터에는 배럴 현상이 발생되어 화상의 저하를 초래하게 되었는데, 이러한 배럴 현상을 제거시키기 위해 본 고안은 수평 주파수 조절단과 수평 출력단 사이에 간단한 회로를 연결 구성시켜 수평 주파수의 변화를 전압으로 나타내어 수평 출력단에 인가시키도록 하므로써 모니터에 발생되는 배럴 현상을 제거하도록 한 것으로, 이하 그의 기술 구성을 첨부된 도면에 따라 설명하면 다음과 같다.In the conventional monitor circuit, a barrel phenomenon occurs in the monitor according to the frequency difference of the horizontal frequency adjusting stage, and the image is degraded. In order to eliminate the barrel phenomenon, the present invention is a simple circuit between the horizontal frequency adjusting stage and the horizontal output stage. By connecting the configuration to indicate the change in the horizontal frequency as a voltage to be applied to the horizontal output stage to eliminate the barrel phenomenon generated in the monitor, the following description of the technical configuration according to the accompanying drawings.
제1도는 본 고안에 따른 모니터의 배럴 현상 제거 회로를 나타낸 것으로 그의 연결 구성을 살펴보면, 수평 주파수 조절단(10)에 저항(R2,R3)을 각각 연결하여 오피앰프(IC1,IC2)의 플러스 입력단에 각각 접속하고, 상기 오피앰프(OP1,OP2)의 마이너스 입력단은 저항(R1)을 거쳐 전원단(+Vcc)에 접속되고 오피앰프(OP1,OP2)의 출력단은 피이드백 저항(R4,R5)을 거쳐 플러스 입력단에 각각 접속되며 동시에 익스클루시브 오아게이트(EX1)의 입력단에 각각 접속되고, 한편 상기 오피앰프(OP1)의 출력단은 익스클루시브 오아게이트(EX1)의 출력단과 함께 익스클루시브 오아게이트(EX2)의 입력단에 각각 접속되고, 익스클루시브 오아게이트(EX2)의 출력단은 트랜지스터(Q1,Q2)와 저항(R6-R8) 및 콘덴서(C1)로 구성된 캐스코드 증폭회로(20)을 거쳐 수평출력단(30)에 접속되는 구성으로, 상기 회로구성의 동작 상태 및 작용 효과를 첨부된 도면에 따라 설명하면, 다음과 같다.1 is a view illustrating a barrel elimination circuit of a monitor according to the present invention. Looking at the connection configuration thereof, the resistors R2 and R3 are connected to the horizontal frequency adjusting stage 10, respectively, and the positive input terminals of the op amps IC1 and IC2 are connected. Respectively, the negative input terminal of the op amps OP1 and OP2 is connected to a power supply terminal (+ Vcc) via a resistor R1, and the output terminals of the op amps OP1 and OP2 are feedback resistors R4 and R5. Respectively connected to the positive input terminal and simultaneously to the input terminal of the exclusive oragate EX1, while the output terminal of the op amp OP1 is coupled with the output terminal of the exclusive oragate EX1. Respectively connected to an input terminal of the gate EX2, and an output terminal of the exclusive ora gate EX2 includes a cascode amplifier circuit 20 composed of transistors Q1 and Q2, resistors R6-R8, and capacitor C1. Connected to the horizontal output terminal 30 via It will be described in accordance with the circuit attached to the operation state and the operation and effect of the configuration drawings, as follows.
본 고안의 동작은 제1도의 회로도에서 보는 바와 같이, 수평 주파수 조절단(10)에서 조절된 주파수가 저항(R2,R3)을 거쳐 오피앰프(OP1,OP2)의 플러스 입력단에 각각 인가되어 전압으로 증폭되게 되고, 상기 오피앰프(OP1,OP2)에서 증폭된 전압(VA,VB)은 익스클루시브 오아게이트(EX1)의 입력단으로 각각 인가되는데, 이때 전압(VA,VB)이 모두 하이(H) 상태일 경우에는 익스클루시브 오아게이트(EX1)의 출력이 로우(L) 상태이므로 이로우(L)상태 신호는 오피앰프(OP1)의 하이(H)상태 출력 신호와 익스클루시브 오아게이트(EX2)에서 조합되어 최종 출력단으로 하이(H)상태의 신호를 출력시켜 캐스코드 증폭회로(20)를 통해 수평 출력단(30)에 인가시켜 모니터의 배럴 현상을 제거시키게 된다.In the operation of the present invention, as shown in the circuit diagram of FIG. 1, the frequency adjusted by the horizontal frequency adjusting stage 10 is applied to the positive input terminals of the op amps OP1 and OP2 via the resistors R2 and R3, respectively, to obtain a voltage. The voltages VA and VB amplified by the op amps OP1 and OP2 are respectively applied to the input terminals of the exclusive oragate EX1, wherein the voltages VA and VB are all high (H). In this state, since the output of the exclusive oragate EX1 is low (L), the low (L) state signal is the high (H) state output signal of the op amp (OP1) and the exclusive oragate (EX2). ) And outputs a signal of the high (H) state to the final output terminal and applied to the horizontal output terminal 30 through the cascode amplifier circuit 20 to eliminate the barrel phenomenon of the monitor.
또한 오피앰프(OP1)의 출력전압(VA)이 로우(L)상태이고 오피앰프(OP2)의 출력전압(VB)이 하이(H) 상태일 경우에도 익스클루시브 오아게이트(EX2)의 출력단으로는 하이(H)상태의 신호를 출력시키므로 캐스코드 증폭회로(20)를 통해 수평 출력단(30)으로 인가시켜 배럴 현상을 제거 시키게 된다.In addition, even when the output voltage VA of the operational amplifier OP1 is low (L) and the output voltage VB of the operational amplifier OP2 is high (H), the output terminal VA of the operational amplifier OP2 is output to the output terminal of the exclusive or gate EX2. Since the output of the high (H) state signal is applied to the horizontal output terminal 30 through the cascode amplifier circuit 20 to eliminate the barrel phenomenon.
따라서 본 고안에 따른 모니터의 배럴 현상 제거 회로는 이상의 설명에서와 같이, 주파수 조절에 따라 증폭 출력된 전압이 수평 출력단에 인가되어 모니터에 발생되는 배럴 현상을 제거시키게 되므로 화상을 안정시켜 시청자에게 최적의 회상 상태를 제공하는 효과를 갖게 된다.Therefore, the barrel phenomenon elimination circuit of the monitor according to the present invention, as described above, is applied to the horizontal output stage by amplified output voltage according to the frequency control to eliminate the barrel phenomenon generated in the monitor, so that the image is stabilized and optimized for the viewer. It has the effect of providing a recall state.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019880010425U KR930006239Y1 (en) | 1988-06-30 | 1988-06-30 | Barrel elimination circuit for monitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019880010425U KR930006239Y1 (en) | 1988-06-30 | 1988-06-30 | Barrel elimination circuit for monitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR900001896U KR900001896U (en) | 1990-01-19 |
| KR930006239Y1 true KR930006239Y1 (en) | 1993-09-15 |
Family
ID=19276919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019880010425U Expired - Lifetime KR930006239Y1 (en) | 1988-06-30 | 1988-06-30 | Barrel elimination circuit for monitor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR930006239Y1 (en) |
-
1988
- 1988-06-30 KR KR2019880010425U patent/KR930006239Y1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| KR900001896U (en) | 1990-01-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| UA0108 | Application for utility model registration |
Comment text: Application for Utility Model Registration Patent event code: UA01011R08D Patent event date: 19880630 |
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| UG1501 | Laying open of application | ||
| A201 | Request for examination | ||
| UA0201 | Request for examination |
Patent event date: 19910614 Patent event code: UA02012R01D Comment text: Request for Examination of Application Patent event date: 19880630 Patent event code: UA02011R01I Comment text: Application for Utility Model Registration |
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| UG1604 | Publication of application |
Patent event code: UG16041S01I Comment text: Decision on Publication of Application Patent event date: 19930823 |
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| E701 | Decision to grant or registration of patent right | ||
| UE0701 | Decision of registration |
Patent event date: 19931211 Comment text: Decision to Grant Registration Patent event code: UE07011S01D |
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| REGI | Registration of establishment | ||
| UR0701 | Registration of establishment |
Patent event date: 19940110 Patent event code: UR07011E01D Comment text: Registration of Establishment |
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