KR930006067Y1 - Automatic accompaniment signal generation circuit of electronic organ - Google Patents

Abstract

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Description

Automatic accompaniment signal generation circuit of electronic organ

1 is a circuit diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

10,20,30,50,80: ANDGATE 40: OAGATE

60,90: flip-flop 70: inverter

The present invention relates to an auto accompaniment signal generating circuit of an electron organ, and more particularly to an auto accompaniment signal generating circuit capable of generating an auto accompaniment signal using a logic circuit.

Currently, an electronic organ is provided with a keyboard key for outputting a sound corresponding to each scale and an auto accompaniment key for outputting chords and bass sounds by pressing one key.

In addition, conventionally, the control of the microcomputer decodes the contents of the keyboard key in the auto accompaniment state, generates and outputs the corresponding code and base data, and simultaneously outputs the code and base change sounds according to the change of the key press. Had used the method.

However, this method has a problem in that the cost increases due to the use of the microcomputer.

Accordingly, an object of the present invention is to provide an auto accompaniment data generating circuit that can perform an auto accompaniment function at a low price since the auto accompaniment function is performed using a logic circuit.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram according to the present invention, a predetermined single through a single finger chord signal input terminal (1), a reset (Reset) signal input terminal (2), the rhythm signal input terminal (3), respectively An AND gate 10 for generating a predetermined auto accompaniment selection signal or generating a clear signal by comparing the input according to the input of the pin code signal, the reset signal and the rhythm signal, and the single pin code signal input terminal 1 and the code. An AND gate 20 for generating a predetermined auto accompaniment selection signal in accordance with a predetermined single pin code signal and a code selection signal through the selection signal input terminal 4, and a predetermined rhythm through the rhythm signal input terminal 3; The AND gate 30 generates a predetermined clock selection signal as a predetermined code selection signal through the signal and code selection signal input terminal 4 is input to both terminals, and the auto accompaniment selection signal of the AND gate 10 or the like. The end gate ( A predetermined auto accompaniment signal is generated by comparing an auto accompaniment selection signal of 20) with an ora gate 40 for outputting an ora ring, and an auto accompaniment selection signal through the ora gate 40 and a predetermined initial state signal. The AND gate 50 and the predetermined clock through the clock signal input terminal 5 are inputted to the clock terminal CK to latch and output the auto accompaniment signal of the AND gate 50 to the input terminal D. A flip-flop 60 and a predetermined clock signal through the clock signal input terminal 5 are outputted to the terminal Q1 and cleared as the clear signal of the AND gate 10 is inputted to the clear terminal CLR1. The inverter 70 for inverting, the auto accompaniment signal through the output terminal Q1 of the flip-flop 60, the output signal of the inverter 70, and the clock selection signal of the AND gate 30 are three terminals, respectively. An AND gate for generating a predetermined second clock signal in response to an input; 80 and the auto-accompaniment signal of the flip-flop 60 are latched to the input terminal D2 as the second clock signal of the AND gate 80 is input to the clock terminal CK2. The flip-flop 90 is outputted to a predetermined system and cleared as the clear signal of the AND gate 10 is inputted to the clock terminal CLR2 and generates and outputs a predetermined initial state signal to the inverted output terminal Q2. It consists of.

Hereinafter, the present invention will be described in detail with reference to FIG. 1.

To enter auto accompaniment, first, a code selection signal is input in a state in which a predetermined single pin code signal is input through the single pin code signal input terminal 1 and a predetermined rhythm signal is input through the rhythm signal input terminal 2. A predetermined code selection signal through the terminal 4 must be input. Secondly, the predetermined single pin code signal through the single pin code signal input terminal 1 and the predetermined code selection signal through the code selection signal input terminal 4 are inputted through the rhythm signal input terminal 3. The rhythm signal of must be input. And a third single finger code signal and a code through the single finger code signal input terminal 1 and the code selection signal input terminal 2 in a state where a predetermined rhythm signal through the rhythm signal input terminal 3 is input. The selection signal must be input.

Looking at the same value when the code selection signal is input in the state where the single pin code signal and the rhythm signal are input as the first condition, the predetermined single through the single pin code signal input terminal 1 and the rhythm signal input terminal 3, respectively. The pink code signal and the rhythm signal, that is, the "high" signal, are input to both terminals of the AND gate 10, respectively.

In addition, since the reset signal input terminal 2 always inputs a predetermined "high" signal to another terminal of the AND gate 10 when performing the auto accompaniment function, the AND gate 10 receives a "high" signal, that is, auto accompaniment. A selection signal is generated and input to one terminal of the oragate 40. The oA gate 40 inputs the input auto accompaniment selection signal to one terminal of the AND gate 50.

On the other hand, in the initial state, the flip-flop 90 has an inverted output terminal. Since the "high" signal is generated and input to the other terminal of the AND gate 50, the AND gate 50 generates an auto accompaniment signal by the signals input to both terminals. The flip-flop 60 latches the auto accompaniment signal as a predetermined clock signal through the clock signal input terminal 5 is input.

On the other hand, the predetermined clock signal through the plug signal input terminal 5 is inverted by the inverter 70 and input to one terminal of the AND gate 80, and the AND gate 80 is output of the flip-flop 60. Input the auto accompaniment signal through the terminal Q1 to the other terminal.

In this state, when a predetermined code selection signal, that is, a "high" signal, through the code selection signal input terminal 4 is input to one terminal of the AND gate 30, the AND gate 30 is connected to the other terminal as a rhythm signal input terminal. Since the predetermined rhythm signal through (3) is input, the AND gate 30 generates a predetermined second clock selection signal and inputs it to another terminal of the AND gate 80. At this time, the AND gate 80 generates a predetermined second clock signal and inputs it to the clock terminal CK2 of the flip-flop 90. Correspondingly, the flip-flop 90 latches the auto accompaniment signal through the output terminal Q1 of the flip-flop 60 to the input terminal D2, and then, through the output terminals Q2 and 6, Output to system

Secondly, when the rhythm signal is input while the single pin code signal and the code selection signal are input, the single pin code code is input through the single pin code signal input terminal 1 and the code selection signal input terminal 4, respectively. As the signal and the code selection signal are input to both terminals of the AND gate 20, the AND gate 20 inputs a predetermined auto accompaniment selection signal to one terminal of the OR gate 40. The oA gate 40 inputs the input auto accompaniment selection signal to the other terminal of the AND gate 50.

In the initial state, the flip-flop 90 outputs a "high" signal to the other terminal of the AND gate 50 through the inverting output terminal Q2.

Therefore, the AND gate 50 inputs both signals to generate an auto accompaniment signal. The flip-flop 60 latches the auto accompaniment signal of the AND gate 50 to the input terminal D1 as a predetermined clock signal through the clock signal input terminal 5 is input to the clock terminal CK. . At this time, the predetermined clock selection signal through the clock signal input terminal 5 is inverted by the inverter 70 and then input to one terminal of the AND gate 80.

On the other hand, when a predetermined rhythm signal through the rhythm signal input terminal 3 is input to one terminal of the AND gate 30 in this state, the AND gate 30 is predetermined through the code selection signal input terminal 4 to the other terminal. Input the code selection signal of. Accordingly, the AND gate 30 generates a " high " signal, that is, a predetermined second clock selection signal, and inputs it to the other terminal of the AND gate 80. At this time, the AND gate 80 generates a predetermined second clock signal and inputs it to the clock terminal Ck2 of the flip-flop 90.

Therefore, the flip-flop 90 receives the automatic variation signal through the output terminal Q1 of the flip-flop 60 as the second clock signal CK2 of the AND gate 80 is input to the clock terminal CK2. The input is input to a predetermined system through the output terminal Q2 and the output line 6.

The third condition is a case where a predetermined single pin code signal and a code selection signal are input while a predetermined rhythm signal is input, and a predetermined rhythm signal through the rhythm signal input terminal 3 is applied to the AND gate 10. A single single code code signal, that is, a "high" signal, is inputted to the AND gate 10 through the code selection signal input terminal 4 through the single pin code signal input terminal 1 in the state of inputting to one terminal. When a code selection signal of is input to one terminal of the AND gate 20 and 30, respectively, a predetermined "high" signal, that is, an auto accompaniment selection signal, of the AND gate 10 is generated to generate one end of the OR gate 40. Enter in characters. The auto accompaniment selection signal through the oragate 40 is input to one terminal of the AND gate 50.

On the other hand, when the initial state is set, the flip-flop 90 generates a predetermined "high" signal through the output terminal Q2 and inputs it to the other terminal of the AND gate 50. Therefore, the AND gate 50 generates a predetermined auto accompaniment selection signal based on the signals input to both terminals. At this time, the flip-flop 60 latches the auto accompaniment selection signal of the AND gate 50 as a predetermined clock selection signal through the clock signal input terminal 5 is input to the clock terminal CK1. The predetermined clock selection signal through the clock signal input terminal 5 is input to one input terminal of the AND gate 80 through the inverter 70.

Meanwhile, the AND gate 30 generates a predetermined second clock selection signal based on a rhythm signal and a code selection signal input to both terminals, and inputs the second clock selection signal to the other terminal of the AND gate 80. Therefore, as the auto accompaniment selection signal through the flip-flop 60 is input to another terminal of the AND gate 80, the AND gate 80 generates a predetermined second clock signal to generate the flip-flop 90. Input to clock terminal CK2.

In this case, the second clock signal of the AND gate 80 is generated when the predetermined clock signal through the clock signal input terminal 5 is downward by the inverter 70, and thus is generated after a half cycle than the predetermined clock signal.

In addition, the flip-flop 90 latches the auto accompaniment selection signal of the flip-flop 60 to the input terminal D2 as the second clock signal is input to the clock terminal CK2, and then output terminal Q2 and Input to the predetermined system via the output line (6).

On the other hand, if any one of the predetermined single pin code signal rhythm signal and the reset signal is "low" to be out of the auto accompaniment state, the AND gate 10 generates a "low" signal, that is, a clear signal, so that the flip-flop 60, Input to the clear terminal (CLR1, CLR2) of (90), respectively. Accordingly, since the flip-flops 60 and 90 are cleared, the flip-flop 90 generates a "low" signal to the output terminal Q2 and supplies the predetermined system through the output line 6 to initialize the predetermined system. Return to the state.

As described above, the present invention performs an auto accompaniment function using a logic circuit, so that the auto accompaniment function can be performed at a low price.

Claims (1)

In the automatic accompaniment signal generation circuit of an electronic organ, a single finger code signal input terminal (1), a reset signal input terminal (2), a rhythm signal input terminal (3), a code selection signal input terminal (4), A predetermined single pin code signal, a reset signal through the clock signal input terminal 5, the single pin code signal input terminal 1, the reset signal input terminal 2, and the rhythm signal input terminal 3; Predetermined through the AND gate 10, the rhythm signal input terminal 3, and the code selection signal input terminal 4 which generate a predetermined auto accompaniment selection signal or a predetermined clear signal as a rhythm signal is input. A predetermined rhythm through the AND gate 20 and the rhythm signal input terminal 3 and the code selection signal input terminal 4 which generate a predetermined clock selection signal as the rhythm signal and the code selection signal are input to both terminals. As the signal and code selection signal are inputted, An AND gate 30 for generating a clock selection signal of the OR gate, an OR accompaniment 40 for inputting an OR accompaniment selection signal of the AND gate 10, and an AUTO accompaniment selection signal of the AND gate 20, and outputting an ORing signal; The AND gate 50 for generating a predetermined auto accompaniment signal by inputting an auto accompaniment selection signal through the oragate 40 and a predetermined initial state signal, and a predetermined clock through the clock signal input terminal 5 As the clock terminal CK1 is input, the auto accompaniment signal of the AND gate 50 is latched to the input terminal D1 and output through the output terminal Q1, and the clear signal of the AND gate 10 is clear terminal ( The flip-flop 60 which is cleared by inputting to the CLR1, the inverter 70 which inverts a predetermined clock signal through the clock signal input terminal 5, and the output terminal Q1 of the flip-flop 60. Auto accompaniment signal through), the output signal of the inverter 70, The AND gate 80 generates a predetermined second clock signal as the clock selection signals of the AND gate 30 are input to three terminals, respectively, and the second clock signal of the AND gate 80 is a clock terminal CK2. By latching the auto accompaniment signal of the flip-flop 60 into the input terminal D2 and inputting it into a predetermined system through the output terminal 6, the clear signal of the AND gate 10 is a clock terminal CLR2. Cleared by inputting the And an electronic accompaniment signal generating circuit comprising: a flip-flop (90) for generating and outputting a predetermined initial state signal.