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KR930001362A - Semiconductor devices - Google Patents

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Publication number
KR930001362A
KR930001362A KR1019920010075A KR920010075A KR930001362A KR 930001362 A KR930001362 A KR 930001362A KR 1019920010075 A KR1019920010075 A KR 1019920010075A KR 920010075 A KR920010075 A KR 920010075A KR 930001362 A KR930001362 A KR 930001362A
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KR
South Korea
Prior art keywords
electrode pads
bonding electrode
row
semiconductor device
rows
Prior art date
Application number
KR1019920010075A
Other languages
Korean (ko)
Inventor
요시유키 코자키
Original Assignee
사토오 켄이치로오
로움 카부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 사토오 켄이치로오, 로움 카부시키가이샤 filed Critical 사토오 켄이치로오
Publication of KR930001362A publication Critical patent/KR930001362A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음No content

Description

반도체 장치Semiconductor devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는, 본 발명의 제1의 실시예에 의한 반도체 칩의 평면도이다.1 is a plan view of a semiconductor chip according to a first embodiment of the present invention.

제2도는, 제1도에서의 Ⅱ-Ⅱ선을 따르는 단면도이다.2 is a cross-sectional view taken along the line II-II in FIG. 1.

제3도는, 제1도에서의 주요부의 확대평면도이다.3 is an enlarged plan view of the main part in FIG.

제4도는, 본 발명의 제2의 실시예에 의한 반도체칩의 평면도이다.4 is a plan view of a semiconductor chip according to a second embodiment of the present invention.

제5도는, 본 발명의 제3의 실시예에 의한 반도체 칩의 평면도이다.5 is a plan view of a semiconductor chip according to a third embodiment of the present invention.

제6도는, 본 발명의 제4의 실시예에 의한 반도체 칩의 평면도이다.6 is a plan view of a semiconductor chip according to a fourth embodiment of the present invention.

Claims (4)

반도체 칩(11)의 표면에서, 적어도 한쪽 가장자리에, 이 반도체 칩(11)의 표면의 소자 회로부(12)에 대한 복수개의 본딩용 전극 패드(14)를 2열로 배열하며, 각 열에서는 본딩용 진극 패드(14)를 일정한 간격으로, 또, 제1열에서의 각 본딩용 전극 패드(14)의 사이 부분에 제2열의 각 본딩용 전극 패드(14)를 배치하는, 즉, 2열의 지그재그 형상으로 배열하여 구성하는 반도체 장치에 있어서, 전기한 제1열의 각 본딩용 전극 페드(14) 중에서 적어도 전기한 제2열의 각 본딩용 전극 패드와 인접하는 부분 및 전기한 제2열의 각 본딩용 전극 패드(14)중에서 적어도 전기한 제1열의 각 본딩용 전극 패드(14)와 인접하는 부분의 양쪽을 사선으로 또는, 원호형상으로 절단하여, 경사부(14C),(14C')를 형성하는 것을 특징으로 하는, 반도체장치.On the surface of the semiconductor chip 11, at least one edge, a plurality of bonding electrode pads 14 for the element circuit portion 12 on the surface of the semiconductor chip 11 are arranged in two rows, in each row for bonding. The two rows of bonding electrode pads 14 are arranged at regular intervals and between the bonding electrode pads 14 in the first row, that is, two rows of zigzag shapes. In the semiconductor device arranged in the form of a semiconductor device, a portion adjacent to each of the bonding electrode pads in at least the second row of the bonding electrode pads 14 in the first row and the bonding electrode pads in the second row. Both of the portions adjacent to each of the bonding electrode pads 14 in the first row that are at least described in (14) are cut diagonally or in an arc shape to form the inclined portions 14C and 14C '. A semiconductor device. 제1항에 있어서, 각 본딩용 전극 패드(14')는 대체적으로 삼각형의 형상을 하며, 다수개의 삼각형의 형상의 본딩용 전극 패드(14')를 서로 역방향으로 한 상태에서, 2열의 지그재그 형상으로 배열하여 구성하는 것을 특징으로 하는, 반도체장치.2. The bonding pads of claim 1, wherein each of the bonding electrode pads 14 'is substantially triangular in shape, and two rows of zig-zag shapes are formed in a state in which the bonding electrode pads 14' in the shape of a plurality of triangles are reversed to each other. A semiconductor device, characterized in that arranged in a configuration. 제1항 또는 제2항에 있어서, 반도체 칩(11)의 중앙에 소자 회로부(12)를 형성하고, 소자 회로부(12)의 좌우양쪽부분에 복수개의 본딩용 전극 패드(14)를 2열의 지그재그 형상으로 배열하여 구성하는 것을 특징으로 하는 반도체창치.The device circuit portion 12 is formed in the center of the semiconductor chip 11, and a plurality of bonding electrode pads 14 are zigzag in the left and right portions of the device circuit portion 12. A semiconductor device comprising a configuration arranged in a shape. 제1항 또는 제2항에 있어서, 반도체 칩(11)의 위에 형성되어 있는 소자 회로부(12)의 둘레를 따라서 복수개의 본딩용 전극 패드(14)를 2열의 지그재그 형상으로 배열하여 구성하는 것을 특징으로 하는, 반도체장치.A plurality of bonding electrode pads 14 are arranged in a zigzag form in two rows along the periphery of the element circuit portion 12 formed on the semiconductor chip 11. A semiconductor device. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019920010075A 1991-06-11 1992-06-10 Semiconductor devices KR930001362A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3139079A JPH04364051A (en) 1991-06-11 1991-06-11 Semiconductor device
JP91-139079 1991-06-11

Publications (1)

Publication Number Publication Date
KR930001362A true KR930001362A (en) 1993-01-16

Family

ID=15236998

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920010075A KR930001362A (en) 1991-06-11 1992-06-10 Semiconductor devices

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Country Link
JP (1) JPH04364051A (en)
KR (1) KR930001362A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010044925A (en) * 1999-11-01 2001-06-05 박종섭 Method for lay out in semiconductor device

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5814892A (en) * 1996-06-07 1998-09-29 Lsi Logic Corporation Semiconductor die with staggered bond pads
US5796171A (en) * 1996-06-07 1998-08-18 Lsi Logic Corporation Progressive staggered bonding pads
JP3328157B2 (en) * 1997-03-06 2002-09-24 シャープ株式会社 Liquid crystal display
JP3623407B2 (en) * 1999-09-14 2005-02-23 三菱電機株式会社 Wiring board
JP3429718B2 (en) 1999-10-28 2003-07-22 新光電気工業株式会社 Surface mounting substrate and surface mounting structure
JP2015088576A (en) * 2013-10-30 2015-05-07 ルネサスエレクトロニクス株式会社 Semiconductor device and method of manufacturing the same
CN111988906B (en) * 2019-05-22 2022-04-29 浙江宇视科技有限公司 Printed circuit board and light emitting diode module board

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01107549A (en) * 1987-10-20 1989-04-25 Mitsubishi Electric Corp Semiconductor integrated circuit device
JPH01298731A (en) * 1988-05-27 1989-12-01 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010044925A (en) * 1999-11-01 2001-06-05 박종섭 Method for lay out in semiconductor device

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Publication number Publication date
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PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19920610

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