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KR920020303A - Multifunction I / O Interface Unit for Data Processing Unit - Google Patents

Multifunction I / O Interface Unit for Data Processing Unit Download PDF

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Publication number
KR920020303A
KR920020303A KR1019910006588A KR910006588A KR920020303A KR 920020303 A KR920020303 A KR 920020303A KR 1019910006588 A KR1019910006588 A KR 1019910006588A KR 910006588 A KR910006588 A KR 910006588A KR 920020303 A KR920020303 A KR 920020303A
Authority
KR
South Korea
Prior art keywords
output
unit
control unit
signal
interface
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Application number
KR1019910006588A
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Korean (ko)
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KR930011442B1 (en
Inventor
김시한
박돈하
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910006588A priority Critical patent/KR930011442B1/en
Publication of KR920020303A publication Critical patent/KR920020303A/en
Application granted granted Critical
Publication of KR930011442B1 publication Critical patent/KR930011442B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Studio Circuits (AREA)

Abstract

내용 없음No content

Description

데이타 처리 장치용 다기능 입출력 인터페이스 장치Multifunction I / O Interface Unit for Data Processing Unit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 시스템 구성도,2 is a system configuration according to the present invention,

제3도는 본 고안의 제어부에 대한 블록도면,3 is a block diagram of a control unit of the present invention,

제4도는 본 발명의 비디오 신호 차단회로에 대한 블록도면이다.4 is a block diagram of a video signal blocking circuit of the present invention.

Claims (2)

적어도 하나 이상의 슬롯(2)을 갖는 메인컴퓨터(1)와, 다수의 외부 장치들의 연결을 위해 상기 슬롯을 통해 장착되는 인터페이스 장치에 있어서, 컴퓨터의 외부기기와의 접속을 위한 각각의 인터페이싱 장치들이 내부 데이타 및 어드레스버스를 통해 공히 연결되고 이들 상호 연결된 인터페이스 장치들의 선택 제어를 위한 제어부(4)를 포함하여 일체 구성되며, 이 제어부(4)는 상기 슬롯(2)을 통해 시스템버스(11)의 신호를 받도록 연결되어 메인컴퓨터와 연락을 갖으며 상기 각각의 인터페이스 장치의 출력은 할당된 연결단자를 통해 각각의 외부기기와 연결되도록 구성되며, 상기 제어부(4)는 I/O번지 선택을 위한 디코더부(41)와, 외부 DIP 스위치 또는 프로그램 제어 모드 선택을 위한 레지스터 및 멀티플랙서로 구성되는 선택부로 포함하여 연결 구성됨을 특징으로 하는 데이타 차리 장치용 다기능 입출력 인터페이스 장치.In a main computer (1) having at least one slot (2) and an interface device mounted through the slot for connecting a plurality of external devices, each of the interfacing devices for connecting to the external device of the computer is internal It is integrally configured, including a control unit 4 for controlling the selection of these interconnected interface devices, which are both connected via data and address buses, and the control unit 4 is connected to the signals of the system bus 11 through the slots 2. Is connected to the main computer and the output of each interface device is configured to be connected to each external device through an assigned connection terminal, and the control unit 4 is a decoder unit for selecting an I / O address. 41, and a selector consisting of a register and a multiplexer for selecting an external DIP switch or a program control mode. Multifunction input-output interface devices for data chari apparatus as ranging. 제1항에 있어서, 비디오 메모리 읽기/쓰기 신호 검출부(101)와, 이 검출부 출력에 따라 계수동작을 행하는 계수부(102)와, 이 계수부 출력과 비디오 메모리의 읽기/쓰기 신호 검출된 값을 비교하여 하이 또는 로우의 펄스를 발생하는 비교부(103)와, 이 비교부 출력과 상기 검출부(101)의 신호를 받아 모니터로 비디오 신호를 공급 또는 차단하도록 하이 또는 로우의 제어신호를 출력하는 래치 구성이 제어부(104)로 구성된 비디오 신호차단 회로를 더욱 포함하는 것을 특징으로 하는 데이타 차리 장치용 다기능 입출력 인터페이스.The video memory read / write signal detection unit (101), the counting unit (102) which performs counting operation in accordance with the output of the detection unit, and the detected values of the counting unit output and the read / write signal of the video memory. A comparator 103 for generating a high or low pulse by comparison, and a latch for outputting a high or low control signal to receive or output a signal from the comparator and the detector 101 and to supply or block a video signal to a monitor The multi-function input / output interface for a data blocking device, wherein the configuration further includes a video signal blocking circuit composed of a control unit 104. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910006588A 1991-04-24 1991-04-24 Multi-function input/output interfacing apparatus for data processor KR930011442B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910006588A KR930011442B1 (en) 1991-04-24 1991-04-24 Multi-function input/output interfacing apparatus for data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910006588A KR930011442B1 (en) 1991-04-24 1991-04-24 Multi-function input/output interfacing apparatus for data processor

Publications (2)

Publication Number Publication Date
KR920020303A true KR920020303A (en) 1992-11-21
KR930011442B1 KR930011442B1 (en) 1993-12-08

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910006588A KR930011442B1 (en) 1991-04-24 1991-04-24 Multi-function input/output interfacing apparatus for data processor

Country Status (1)

Country Link
KR (1) KR930011442B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020060791A (en) * 2001-01-12 2002-07-19 엘지이노텍 주식회사 External selectable rt address circuit for integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020060791A (en) * 2001-01-12 2002-07-19 엘지이노텍 주식회사 External selectable rt address circuit for integrated circuit

Also Published As

Publication number Publication date
KR930011442B1 (en) 1993-12-08

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