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KR920017227A - Interlayer contact structure of semiconductor device and manufacturing method thereof - Google Patents

Interlayer contact structure of semiconductor device and manufacturing method thereof Download PDF

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Publication number
KR920017227A
KR920017227A KR1019910001977A KR910001977A KR920017227A KR 920017227 A KR920017227 A KR 920017227A KR 1019910001977 A KR1019910001977 A KR 1019910001977A KR 910001977 A KR910001977 A KR 910001977A KR 920017227 A KR920017227 A KR 920017227A
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insulating film
forming
wiring
via hole
compensation band
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KR1019910001977A
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Korean (ko)
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김종복
이규필
양원석
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김광호
삼성전자 주식회사
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Priority to KR1019910001977A priority Critical patent/KR920017227A/en
Priority to ITMI911148A priority patent/IT1248595B/en
Priority to GB9108853A priority patent/GB2252668A/en
Priority to DE4113775A priority patent/DE4113775A1/en
Priority to JP3124853A priority patent/JPH0613468A/en
Priority to FR9105457A priority patent/FR2672430A1/en
Publication of KR920017227A publication Critical patent/KR920017227A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01056—Barium [Ba]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음No content

Description

반도체장치의 층간콘택 구조 및 그 제조방법Interlayer contact structure of semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 반도체장치의 층간콘택구조,2 is an interlayer contact structure of a semiconductor device according to the present invention,

제3A도 내지 제3E도는 본 발명의 일 실시예에 의한 반도체장치의 층간콘택법을 도시한 단면도,3A to 3E are cross-sectional views showing an interlayer contact method of a semiconductor device according to one embodiment of the present invention;

제4A도 내지 4B도는 본 발명의 다른 실시예에 의한 반도체장치의 층간콘택법을 도시한 단면도.4A to 4B are cross-sectional views showing an interlayer contact method of a semiconductor device according to another embodiment of the present invention.

Claims (20)

그 표면에 단차에 의한 굴곡이 형성된 반도체기판상에 비아홀을 통한 층간콘택을 형성하는데 있어서, 층간절연막에 형성된 비아홀, 상기 비아홀을 통해 접촉되는 하층배선과 상층배선, 및 상기 비아홀의 수직하단부 및 상기 하층배선하에 형성되는 보상대로 이루어지는 것을 특징으로 하는 반도체장치의 층간콘택구조.In forming an interlayer contact through a via hole on a semiconductor substrate having a stepped curvature on its surface, a via hole formed in an interlayer insulating film, a lower layer wiring and an upper layer wiring contacting through the via hole, and a vertical lower end portion and the lower layer of the via hole. An interlayer contact structure of a semiconductor device, characterized by comprising a compensation band formed under wiring. 제1항에 있어서, 상기 보상대를 상기 바이홀과 그 크기가 유사한 것을 특징으로 하는 반도체장치의 층간콘택구조.The interlayer contact structure of a semiconductor device according to claim 1, wherein said compensation band is similar in size to said bi-hole. 제1항에 있어서, 상기 보상대는 상기 비아홀의 크기보다 더 큰 것을 특징으로 하는 반도체장치의 층간콘택구조.The interlayer contact structure of claim 1, wherein the compensation band is larger than a size of the via hole. 제1항에 있어서, 상기 보상대는 상기 비아홀의 수직하단부에서 고립된 모양으로 형성되는 것을 특징으로 하는 반도체장치의 층간콘택구조.The interlayer contact structure of claim 1, wherein the compensation band is formed in an isolated shape at a vertical lower end of the via hole. 제1항에 있어서, 상기 보상대는 상기 비아홀의 수작하단부에서 다른 배선과 연결되는 모양으로 형성되는 것을 특징으로 하는 반도체장치의 층간콘택구조.The interlayer contact structure of claim 1, wherein the compensation band is formed to be connected to another wiring at the lower end of the via hole. 제1항에 있어서, 상기 보상대는 상기 하층배선과 절연층을 사이에 두고 형성되는 것을 특징으로 하는 반도체장치의 층간콘택구조.The interlayer contact structure of claim 1, wherein the compensation band is formed with the lower wiring and the insulating layer interposed therebetween. 제1항에 있어서, 상기 보상대는 상기 표면단차를 보상하는 정도의 두께로 형성되는 것을 특징으로 하는 반도체장치의 층간콘택구조.The interlayer contact structure of claim 1, wherein the compensation band is formed to have a thickness compensating for the surface level difference. 그 표면에 단차에 의한 굴곡이 형성된 반도체기판 상에 다층배선을 형성하는데 있어서, 상기 반도체기판 전면에 제1절연막을 도포하는 공정; 상기 제1절연막상에 제1물질을 형성하는 공정; 상기 제1물질상에 감광막 패턴을 형성한 후 사진식각공정을 행하므로 비아홀 수직하단부에 보상대를 형성하는 공정; 상기 보상대가 형성된 제1절연막 전면에 제2절연막을 도포하는 공정; 상기 제2절연막 상에 도전물질을 증착한 후 패터닝하여 하층배선을 형성하는 공정; 상기 하층배선이 형성된 제2절연막 전면에 층간절연막을 형성하는 공정; 상기 층간절연막에 비아홀을 형성하는 공정, 및 상기 비아홀을 매몰하면서 상기 하층뱃너과 접촉하는 상층배선을 형성하는 공정으로 이루어지는 것을 특징으로 하는 반도체장치의 층간콘택법.Forming a multi-layered wiring on a semiconductor substrate having a curvature due to a step on its surface, comprising: applying a first insulating film to the entire surface of the semiconductor substrate; Forming a first material on the first insulating film; A photolithography process is performed after the photoresist pattern is formed on the first material, thereby forming a compensation band at a lower vertical portion of the via hole; Applying a second insulating film to the entire surface of the first insulating film on which the compensation band is formed; Depositing a conductive material on the second insulating layer and patterning the conductive material to form a lower layer wiring; Forming an interlayer insulating film on an entire surface of the second insulating film on which the lower layer wiring is formed; Forming a via hole in said interlayer insulating film, and forming an upper layer wiring contacting said lower layer banner while embedding said via hole. 제8항에 있어서, 상기 제1물질은 도전물질인 것을 특징으로 하는 반도체장치의 층간콘택법.The method of claim 8, wherein the first material is a conductive material. 제9항에 있어서, 상기 보상대는 전기적으로 플로우팅(floating)된 것을 특징으로 하는 반도체장치의 층간콘택법.10. The method of claim 9, wherein the compensation band is electrically floating. 제8항에 있어서, 상기 제1물질은 절연물질인 것을 특징으로 하는 반도체장치의 층간콘택법.The method of claim 8, wherein the first material is an insulating material. 제8항에 있어서, 상기 보상대는 상기 비아홀 주변의 배선을 연장하여 형성하는 것을 특징으로 하는 반도체장치의 층간콘택법.9. The method of claim 8, wherein the compensation band is formed by extending a wiring around the via hole. 제12항에 있어서, 상기 배선은 소자동작에 필요한 도전체라인(line)인 것을 특징으로 하는 반도체장치의 층간콘택법.13. The interlayer contact method of claim 12, wherein the wiring is a conductor line required for device operation. 제8항에 있어서, 상기 보상대는 소작동작에는 필하지 않지만 본 발명의 목적을 수행하기 위해 별도로 형성된 전도물질이나 절연물질 중의 어느 하나인 것을 특징으로 하는 반도체장치의 층간콘택법.10. The method of claim 8, wherein the compensation band is one of a conductive material and an insulating material that are not necessary for small operation but are separately formed for the purpose of the present invention. 제8항에 있어서, 상기 층간절연막은 평탄화된 것을 특징으로 하는 반도체장치의 층간콘택법.The interlayer contact method of claim 8, wherein the interlayer insulating film is planarized. 제8항에 있어서, 상기 비아홀은 주별패턴에 의해 그 층간절연막의 깊이가 깊은 곳에 형성되는 것을 특징으로 하는 반도체장치의 층간콘택법.9. The interlayer contact method of claim 8, wherein the via hole is formed at a deep depth of the interlayer insulating film by a weekly pattern. 제8항에 있어서, 상기 비아홀은 상기 반도체기판의 표면으로부터 층간절연막의 깊이가 일정한 곳에 형성되는 것을 특징으로 하는 반도체장치의 층간콘택법.The interlayer contact method of claim 8, wherein the via hole is formed at a constant depth of the interlayer insulating film from a surface of the semiconductor substrate. 그 표면에 단차에 의한 굴곡이 형성된 반도체기판 상에 배선을 형성하는데 있어서, 상기 반도체기판 전면에 제1절연막을 도포하는 공정; 상기 제1절연막상에 제1물질을 형성하는 공정; 상기 제1물질을 패터닝하여 상기 굴곡에 의해 형성된 오목한 부분중 배선이 형성될 영역에 보상대를 형성하는 공정; 상기 보상대가 형성된 제1절연막 전면에 제2절연막을 형성하는 공정, 및 상기 제2절연막 상에 도전물질을 증착한 후 패터닝하므로 배선을 형성하는 공정으로 이루어지는 것을 특징으로 하는 반도체장치의 층간콘택법.Forming a wiring on a semiconductor substrate having a curvature due to a step on its surface, comprising: applying a first insulating film to the entire surface of the semiconductor substrate; Forming a first material on the first insulating film; Patterning the first material to form a compensation band in a region in which a wiring is to be formed among the concave portions formed by the bending; Forming a second insulating film on the entire surface of the first insulating film on which the compensation band is formed; and forming a wiring by depositing and patterning a conductive material on the second insulating film. 그 표면에 단차에 의한 굴곡이 형성된 반도체기판 상에 다층배선을 형성하는데 있어서, 상기 반도체기판 전면에 제1물질을 형성하는 공정; 상기 제1물질상에 감광막 패턴을 형성한 후 사진식각공정을 행하므로 비아홀 수직하단부에 보상대를 형성하는 공정; 상기 보상대가 형성된 제1절연막 전면에 제2절연막을 도포하는 공정; 상기 제2절연막 상에 도전물질을 증착한 후 패턴닝하여 하층배선을 형성하는 고정; 상기 하층배선이 형성된 제2절연막 전면에 층간절연막을 형성하는 공정; 상기 층간절연막에 상기 보상대와 수직선상에 위치하도록 비아홀을 형성하는 고정, 및 상기 비아홀을 매몰하면서 상기 하층배선과 접촉하는 상층배선을 형성하는 공정으로 이루어지는 것을 특징으로 하는 반도체장치의 층간콘택법.Forming a multi-layered wiring on a semiconductor substrate having curvature due to a step on its surface, comprising: forming a first material on the entire surface of the semiconductor substrate; A photolithography process is performed after the photoresist pattern is formed on the first material, thereby forming a compensation band at a lower vertical portion of the via hole; Applying a second insulating film to the entire surface of the first insulating film on which the compensation band is formed; Fixing a patterned layer by depositing a conductive material on the second insulating layer and forming a lower layer wiring; Forming an interlayer insulating film on an entire surface of the second insulating film on which the lower layer wiring is formed; And forming a via hole in the interlayer insulating film so as to be in a vertical line with the compensation band, and forming an upper wiring in contact with the lower wiring while the via hole is buried. 제19항에 있어서, 상기 제1물질을 절연물질인 것을 특징으로 하는 반도체장치의 층간콘택법.20. The method of claim 19, wherein the first material is an insulating material. ※참고사항:최초출원 내용에 의하여 공개하는 것임.※ Note: This is to be disclosed based on the first application.
KR1019910001977A 1991-02-05 1991-02-05 Interlayer contact structure of semiconductor device and manufacturing method thereof KR920017227A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019910001977A KR920017227A (en) 1991-02-05 1991-02-05 Interlayer contact structure of semiconductor device and manufacturing method thereof
ITMI911148A IT1248595B (en) 1991-02-05 1991-04-24 CONTACT STRUCTURE OF A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
GB9108853A GB2252668A (en) 1991-02-05 1991-04-25 Interlayer contact structure
DE4113775A DE4113775A1 (en) 1991-02-05 1991-04-26 INTERLAY CONTACT STRUCTURE OF A SEMICONDUCTOR DEVICE AND METHOD FOR THEIR PRODUCTION
JP3124853A JPH0613468A (en) 1991-02-05 1991-04-26 Interlayer contact structure of semiconductor device and manufacture thereof
FR9105457A FR2672430A1 (en) 1991-02-05 1991-05-03 Inter-layer contact structure of a semiconductor device and method of fabricating it

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Application Number Priority Date Filing Date Title
KR1019910001977A KR920017227A (en) 1991-02-05 1991-02-05 Interlayer contact structure of semiconductor device and manufacturing method thereof

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KR920017227A true KR920017227A (en) 1992-09-26

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JP (1) JPH0613468A (en)
KR (1) KR920017227A (en)
DE (1) DE4113775A1 (en)
FR (1) FR2672430A1 (en)
GB (1) GB2252668A (en)
IT (1) IT1248595B (en)

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US9887157B2 (en) 2013-08-21 2018-02-06 SK Hynix Inc. Semiconductor device and method of manufacturing the same

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* Cited by examiner, † Cited by third party
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FR2672430A1 (en) 1992-08-07
ITMI911148A0 (en) 1991-04-24
GB2252668A (en) 1992-08-12
IT1248595B (en) 1995-01-19
GB9108853D0 (en) 1991-06-12
ITMI911148A1 (en) 1992-10-24
JPH0613468A (en) 1994-01-21
DE4113775A1 (en) 1992-08-13

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