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KR920015363A - TTL input buffer circuit - Google Patents

TTL input buffer circuit Download PDF

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Publication number
KR920015363A
KR920015363A KR1019910001028A KR910001028A KR920015363A KR 920015363 A KR920015363 A KR 920015363A KR 1019910001028 A KR1019910001028 A KR 1019910001028A KR 910001028 A KR910001028 A KR 910001028A KR 920015363 A KR920015363 A KR 920015363A
Authority
KR
South Korea
Prior art keywords
output terminal
ground
terminal
input
sensing means
Prior art date
Application number
KR1019910001028A
Other languages
Korean (ko)
Inventor
배명호
안계호
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910001028A priority Critical patent/KR920015363A/en
Priority to DE4128736A priority patent/DE4128736A1/en
Priority to JP3244104A priority patent/JPH04259993A/en
Priority to GB9118650A priority patent/GB2252213A/en
Priority to CN91108636A priority patent/CN1063588A/en
Publication of KR920015363A publication Critical patent/KR920015363A/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/088—Transistor-transistor logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

내용 없음No content

Description

TTL입력 버퍼회로TTL input buffer circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 TTL 입력 버퍼회로의 구성도.3 is a block diagram of a TTL input buffer circuit of the present invention.

Claims (2)

TTL레벨의 데이타를 수신하는 입력단자와, 제1출력단자 및 제2출력단자와, 상기 입력단자와 제1출력단자 사이에 접속되어 입력 TTL레벨을 감지하는 수단과, 상기 제1출력단자와 제2출력단자 사이에 접속되어 상기 감지수단의 출력 논리레벨을 결정하여 드라이브하는 수단과, 상기 감지수단 및 드라이브수단으로 전원공급을 위한 전원단자를 구비한 TTL입력버퍼 회로에 있어서, 접지패드와, 상기 감지수단과 상기 접지패드사이에 연결되어 상기 감지수단으로 접지전위를 공급하는 제1접지라인과, 상기 드라이브 수단과 상기 접지패드 사이에 연결되어 상기 드라이브 수단으로 접지전위를 공급하는 제2접지라인으로 분리배치 구성하여 상기 드라이브 수단에서 발생하는 접지노이즈가 상기 감지수단으로 유입됨을 방지하도록 동작함을 특징으로 하는 TTL입력버퍼회로.Means for detecting an input TTL level by being connected between an input terminal for receiving data of a TTL level, a first output terminal and a second output terminal, between the input terminal and the first output terminal, and the first output terminal and the first output terminal. A TTL input buffer circuit having a power terminal for supplying power to the sensing means and the drive means, the means for determining and driving the output logic level of the sensing means connected between two output terminals, comprising: a ground pad; A first ground line connected between a sensing means and the ground pad to supply a ground potential to the sensing means, and a second ground line connected between the drive means and the ground pad to supply a ground potential to the drive means; TTL input, characterized in that the operation arranged to prevent the ground noise generated in the drive means to flow into the sensing means by configuring a separate arrangement Buffer circuit. TTL레벨의 데이타를 수신하는 입력단자와, 제1출력단자 및 제2출력단자와, 상기 입력단자와 제1출력단자 사이에 접속되어 입력 TTL레벨을 감지하는 수단과, 상기 제1출력단자와 제2출력단자 사이에 접속되어 상기 감지수단의 출력 논리레벨을 결정하여 드라이브하는 수단과, 상기 감지수단 및 드라이브 수단으로 전원공급을 위한 전원단자를 구비한 TTL입력버퍼회로에 있어서, 각각 독립적으로 분리배치되는 제1접지패드 및 제2접지패드와, 상기 감지수단과 상기 제1접지패드 사이에 연결되어 상기 감지수단으로 접지전위를 공급하는 제1접지라인과, 상기 드라이브 수단과 상기 제2접지패드 사이에 연결되어 상기 드라이브 수단으로 접지전위를 공급하는 제2접지라인으로 구성됨을 특징으로 하는 TTL입력버퍼회로.Means for detecting an input TTL level by being connected between an input terminal for receiving data of a TTL level, a first output terminal and a second output terminal, between the input terminal and the first output terminal, and the first output terminal and the first output terminal. In the TTL input buffer circuit connected between two output terminals and having a means for determining and driving the output logic level of the sensing means and a power terminal for supplying power to the sensing means and the drive means, each of which is independently arranged A first grounding pad and a second grounding pad, a first grounding line connected between the sensing means and the first grounding pad to supply a ground potential to the sensing means, and between the drive means and the second grounding pad. And a second ground line connected to the second ground line for supplying a ground potential to the drive means. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910001028A 1991-01-22 1991-01-22 TTL input buffer circuit KR920015363A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019910001028A KR920015363A (en) 1991-01-22 1991-01-22 TTL input buffer circuit
DE4128736A DE4128736A1 (en) 1991-01-22 1991-08-29 TTL INPUT BUFFER
JP3244104A JPH04259993A (en) 1991-01-22 1991-08-30 Ttl input buffer circuit
GB9118650A GB2252213A (en) 1991-01-22 1991-08-30 TTL input buffer
CN91108636A CN1063588A (en) 1991-01-22 1991-08-31 Transistor-Transistor Logic Input Buffers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910001028A KR920015363A (en) 1991-01-22 1991-01-22 TTL input buffer circuit

Publications (1)

Publication Number Publication Date
KR920015363A true KR920015363A (en) 1992-08-26

Family

ID=19310147

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910001028A KR920015363A (en) 1991-01-22 1991-01-22 TTL input buffer circuit

Country Status (5)

Country Link
JP (1) JPH04259993A (en)
KR (1) KR920015363A (en)
CN (1) CN1063588A (en)
DE (1) DE4128736A1 (en)
GB (1) GB2252213A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100392556B1 (en) * 1994-01-31 2003-11-12 주식회사 하이닉스반도체 Input buffer for cmos circuit
JP3008924B2 (en) 1998-04-10 2000-02-14 富士電機株式会社 Power element drive circuit

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52146274A (en) * 1976-05-31 1977-12-05 Toshiba Corp Output circuit
JPS5851561A (en) * 1981-09-24 1983-03-26 Hitachi Ltd Semiconductor integrated circuit device
JPS59149427A (en) * 1983-02-16 1984-08-27 Mitsubishi Electric Corp semiconductor equipment
GB2178618A (en) * 1985-07-27 1987-02-11 Stc Plc Input buffer circuit for static ram
US4698526A (en) * 1985-10-17 1987-10-06 Inmos Corporation Source follower CMOS input buffer
CA2008749C (en) * 1989-06-30 1999-11-30 Frank Wanlass Noise rejecting ttl to cmos input buffer

Also Published As

Publication number Publication date
JPH04259993A (en) 1992-09-16
GB2252213A (en) 1992-07-29
CN1063588A (en) 1992-08-12
GB9118650D0 (en) 1991-10-16
DE4128736A1 (en) 1992-07-30

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A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19910122

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19910122

Comment text: Request for Examination of Application

PG1501 Laying open of application
E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 19930818

Patent event code: PE09021S01D

PC1902 Submission of document of abandonment before decision of registration
SUBM Surrender of laid-open application requested