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KR920013940A - 상태 평가량 기억장치 - Google Patents

상태 평가량 기억장치 Download PDF

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Publication number
KR920013940A
KR920013940A KR1019900020808A KR900020808A KR920013940A KR 920013940 A KR920013940 A KR 920013940A KR 1019900020808 A KR1019900020808 A KR 1019900020808A KR 900020808 A KR900020808 A KR 900020808A KR 920013940 A KR920013940 A KR 920013940A
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South Korea
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KR1019900020808A
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KR930004862B1 (ko
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박일근
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정용문
삼성전자 주식회사
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Priority to KR1019900020808A priority Critical patent/KR930004862B1/ko
Priority to JP3127960A priority patent/JP2717032B2/ja
Priority to US07/723,192 priority patent/US5272706A/en
Publication of KR920013940A publication Critical patent/KR920013940A/ko
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Publication of KR930004862B1 publication Critical patent/KR930004862B1/ko
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Error Detection And Correction (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Dc Digital Transmission (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

내용 없음

Description

상태 평가량 기억장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 제1도에 따른 바이터비 복호기에 채용된 가산비교 선택부와 상태 평가량 기억부의 상세 구성도, 제3도는 제1도에 따른 부호비 R=1/2, 구속장 K=3인 경우의 격자 상태도.

Claims (4)

  1. 입력버퍼(100)와 지로평가량 계산부(200)와, 가산비교선택부(300)와, 상태평가량 기억부(400)와, 경로추적 논리부(500)와 경로기억부(600) 및 주클럭발생부(700)를 구비한 바이터비 복호기에 있어서, 상기 상태평가량 기억부 (400)와 상기 가산비교선택부(300)에서 전송되는 현상태 평가량의 이전상태를 기억시키는 제1,2지연기(SR0, SR1)와, 상기 가산비교선택부(300)에서 전송되는 현상태 평가량을 기억시키는 제3,4지연기(SR2, SR3)와, 다음 데이타가 입력되는 다음 시점에서 상기 제1,2지연기(SR0, SR1)가 현상태 평가량을 기억하도록 절체시키는 제1,2절체기(SW1, SW2)와, 다음 데이타가 입력되는 다음 시점에서 상기 제3,4지연기 (SR2, SR3)가 이전상태의 상태평가량을 기억하도록 절체시키는 제3,4절체기 (SW3, SW4)와, 시점변화에 따라 이전 상태평가량으로 사용되는 제1, 2, 3, 4지연기 (SR0, SR1, SR2, SR3)의 출력신호를 상기 가산비교선택부(300)의 입력단으로 전송하는 제5,6절체기(SW5, SW6)와, 상기 제1,2,3,4지연기(SR0, SR1, SR2, SR3)의 각 상태를 계산하는 기본주기의 클럭신호를 순차적으로 공급하는 제7, 8, 9, 10절체기 (SW7, SW8, SW9, SW10)를 포함함을 특징으로 하는 상태평가량 기억장치.
  2. 제1항에 있어서, 상태 평가량 기억수단인 지연기의 길이를 어는 한 시점에서 계산해야 되는 총 상태수(S=2k-1)를 한 상태로 도달되는 지로의 갯수(B=2n-1)로 나눈값(S/B)으로 설정함을 특징으로 하는 상태평가량 기억장치.
  3. 제1항에 있어서, 상태평가량 기억수단이 지연기의 총 갯수를 어느 한 시점에서 현 상태에 도달하는 지로의 갯수(B)의 두배로 설정하여 각각 이전상태 평가량 기억수단과 현상태 평가량 기억수단으로 사용함을 특징으로 하는 상태평가량 기억장치.
  4. 제1항에 있어서, 상태평가량 기억수단의 각지연기에 공급되는 이동 동작클럭 (M/2 CLOCK, M/2 CLOCK)은 주상태 평가계산 기본클럭(INPUT CLOCK)을 지로 갯수(B)로 나눈후 주클럭(MAINCLOCK)의 주기에 따라 순차적으로 공급하여 각 지연기에 계산된 평가량이 분할 기억됨을 특징으로 하는 상태평가량 기억장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900020808A 1990-12-17 1990-12-17 상태 평가량 기억장치 Expired - Fee Related KR930004862B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019900020808A KR930004862B1 (ko) 1990-12-17 1990-12-17 상태 평가량 기억장치
JP3127960A JP2717032B2 (ja) 1990-12-17 1991-05-30 ビタビ復号器
US07/723,192 US5272706A (en) 1990-12-17 1991-06-28 State metric memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900020808A KR930004862B1 (ko) 1990-12-17 1990-12-17 상태 평가량 기억장치

Publications (2)

Publication Number Publication Date
KR920013940A true KR920013940A (ko) 1992-07-30
KR930004862B1 KR930004862B1 (ko) 1993-06-09

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KR1019900020808A Expired - Fee Related KR930004862B1 (ko) 1990-12-17 1990-12-17 상태 평가량 기억장치

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US (1) US5272706A (ko)
JP (1) JP2717032B2 (ko)
KR (1) KR930004862B1 (ko)

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US5327440A (en) * 1991-10-15 1994-07-05 International Business Machines Corporation Viterbi trellis coding methods and apparatus for a direct access storage device
US5432803A (en) * 1992-04-30 1995-07-11 Novatel Communications, Ltd. Maximum likelihood convolutional decoder
JPH06338808A (ja) * 1993-05-28 1994-12-06 Matsushita Electric Ind Co Ltd 加算比較選択装置
US5465275A (en) * 1993-11-16 1995-11-07 At&T Ipm Corp. Efficient utilization of present state/next state registers
US5619514A (en) * 1994-12-29 1997-04-08 Lucent Technologies Inc. In-place present state/next state registers
EP0769853B1 (de) * 1995-10-21 2001-10-04 Micronas GmbH Logischer Block für einen Viterbi-Decoder
US5844947A (en) * 1995-12-28 1998-12-01 Lucent Technologies Inc. Viterbi decoder with reduced metric computation
JPH09232973A (ja) * 1996-02-28 1997-09-05 Sony Corp ビタビ復号器
US5881075A (en) * 1996-03-18 1999-03-09 Samsung Electronics Co., Ltd. Viterbi decoder
KR100484127B1 (ko) * 1997-08-07 2005-06-16 삼성전자주식회사 비터비디코더
CA2306835A1 (en) * 1997-11-03 1999-05-14 Harris Corporation A field programmable radio frequency communications equipment including a configurable if circuit and method therefor
KR100311504B1 (ko) * 1998-01-22 2001-11-22 서평원 비터비디코더의스태이트메트릭메모리및이를이용한복호화방법
US6477680B2 (en) * 1998-06-26 2002-11-05 Agere Systems Inc. Area-efficient convolutional decoder
US6219389B1 (en) * 1998-06-30 2001-04-17 Motorola, Inc. Receiver implemented decoding method of selectively processing channel state metrics to minimize power consumption and reduce computational complexity
US6236692B1 (en) 1998-07-09 2001-05-22 Texas Instruments Incorporated Read channel for increasing density in removable disk storage devices
GB2341764B (en) * 1998-09-19 2003-09-10 Mitel Semiconductor Ltd Read arrangements
TWI228654B (en) * 2003-07-11 2005-03-01 Mediatek Inc Non-binary Viterbi data processing system and method
TWI313107B (en) * 2003-11-24 2009-08-01 Unified viterbi/turbo decoder for mobile communication systems
US20050157823A1 (en) * 2004-01-20 2005-07-21 Raghavan Sudhakar Technique for improving viterbi decoder performance
US7734992B2 (en) * 2004-04-07 2010-06-08 Panasonic Corporation Path memory circuit
US20080152044A1 (en) * 2006-12-20 2008-06-26 Media Tek Inc. Veterbi decoding method for convolutionally encoded signal
US8499229B2 (en) 2007-11-21 2013-07-30 Micro Technology, Inc. Method and apparatus for reading data from flash memory
US8386895B2 (en) 2010-05-19 2013-02-26 Micron Technology, Inc. Enhanced multilevel memory
US8904266B2 (en) * 2010-08-10 2014-12-02 Nxp, B.V. Multi-standard viterbi processor
US8433975B2 (en) 2010-08-13 2013-04-30 Nxp B.V. Bitwise reliability indicators from survivor bits in Viterbi decoders

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JPS6081925A (ja) * 1983-10-12 1985-05-10 Nec Corp 誤り訂正装置
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JPH03195129A (ja) * 1989-12-22 1991-08-26 Mitsubishi Electric Corp 最尤系列推定装置

Also Published As

Publication number Publication date
US5272706A (en) 1993-12-21
JP2717032B2 (ja) 1998-02-18
JPH0653844A (ja) 1994-02-25
KR930004862B1 (ko) 1993-06-09

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