KR920010422A - Micro computer - Google Patents

Abstract

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Description

Micro computer

Since this is an open matter, no full text was included.

1 is a block diagram of one embodiment of a microcomputer according to the present invention;

2 is a block diagram of a detailed example of a central processing unit in the microcomputer of this embodiment;

3 is an explanatory diagram of the basic form of the command format.

Claims (8)

A microcomputer that emulates an emulation target instruction as a predetermined instruction included in a macro instruction set into an emulation instruction sequence as another macro instruction, wherein the emulation instruction has a space separate from other macro instructions, and the fetched instruction is an emulation target instruction. And control means having a logic for converting the command space into the emulation command space when it is determined whether to approve or not and detects an emulation target command. The method according to claim 1, wherein the control means further determines logic for fetching the command as a return command as an emulation command and, when detecting the return command, converts the emulation command space into another macro command space. Micro computer made up including. The method according to claim 1 or 2, further comprising a program counter and a condition code register dedicated for emulation instructions and other macro instructions, wherein the control means switches the registers according to the change of the instruction space. A microcomputer made by adding logic for selection. The method according to any one of claims 1 to 3, wherein temporal registers available only for execution of emulation instructions are provided, and said control means emulates those temporal registers in accordance with the detection of an emulation target instruction. A microcomputer consisting of additional logic that makes additional resources available for instruction execution. The emulation instruction register according to any one of claims 1 to 4, wherein the instruction register receives an emulation target instruction and maintains it, and at the same time provides an emulation instruction register capable of transmitting all or part of the emulation target instruction held by the instruction register to the operation unit. Microcomputer made by doing. The method according to any one of claims 1 to 5, wherein the control means further comprises logic for calculating the address of the corresponding emulation instruction using all or part of the operation code in the emulation target instruction. Microcomputer. The control means according to any one of claims 1 to 6, each having a data memory space dedicated for execution of instructions in an emulation instruction space and instructions for execution in other macro instruction spaces. A microcomputer comprising logic for switching and controlling the data memory space in accordance with the switching of the command space. The control means according to claim 2, wherein the control means provides an instruction save register for storing the next instruction fetched in an instruction cycle parallel thereto when the control means detects an emulation cost instruction in the instruction decode cycle. And a logic for returning the value of the instruction save register to the instruction register when the return instruction is detected. ※ Note: The disclosure is based on the initial application.