KR920009029B1 - Apparatus which drives a color liquid crystal display panel and the method - Google Patents

Abstract

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Description

Color liquid crystal display panel drive device and method

1A to 1C are block diagrams showing the structure of a liquid crystal panel according to the prior art.

2 is a block diagram showing an electrical configuration of a liquid crystal drive circuit according to the prior art.

3 is a block diagram showing an electrical configuration of a line memory circuit for each color in the prior art.

4 is a block diagram showing an electrical configuration of a liquid crystal drive circuit according to an embodiment of the present invention.

5 is a block diagram showing an electrical configuration of the used line memory circuit of this embodiment.

6 is a time chart illustrating the read operation of the embodiment.

7 is a time chart illustrating the recording operation of the embodiment.

8 is a diagram showing a scanning order and a polarity inversion of a gate line in a double speed sequential method.

9 shows the scanning order and polarity inversion of gate lines in an interlaced manner.

10 is a diagram illustrating a scanning order and polarity inversion of a gate line in a high speed line sequential method.

11 is a diagram showing a schematic configuration of a liquid crystal panel.

FIG. 12 shows the color filter arrangement of the liquid crystal panel of FIG.

FIG. 13 is a diagram showing an example of the configuration of a source driver for driving the liquid crystal panel shown in FIG.

14 is a diagram showing a characteristic structure of a line memory circuit for deriving a video signal for a high speed line sequential method according to another embodiment of the present invention.

FIG. 15 is a block diagram showing a configuration for deriving two sets of video signal data for odd gate lines and even gate lines from a video signal of one horizontal period in the line memory circuit shown in FIG.

FIG. 16 is a timing chart showing the operation of the A / D converter and the three state buffer shown in FIG.

FIG. 17 is a block diagram showing an example of a specific configuration of a data column conversion circuit of the line memory circuit shown in FIG.

FIG. 18 is a timing chart showing the operation of the data column conversion circuit shown in FIG. 17. FIG.

Fig. 19A is a timing chart showing the operation of writing a data string converted into a data string of one column of a data string conversion circuit into a memory.

19B is a diagram schematically showing a write operation of data in each memory and a recording area in each memory.

FIG. 20A is a timing chart showing the operation of reading data from the memory shown in FIG.

FIG. 20B is a diagram schematically showing an operation shown in the timing chart of FIG. 20A in the memory area.

21 is a diagram showing an example of the configuration of a polarity switching circuit included in the line memory circuit shown in FIG.

FIG. 22 is a timing chart showing the operation of the polarity switching circuit shown in FIG.

FIG. 23 is a diagram showing an example of a block configuration for converting one column of data columns included in the line memory circuit shown in FIG. 14 into a video signal corresponding to R, G, and B colors.

24 is a timing chart showing the timing chart shown in FIG. 23, the operation of each D / A converter, and an operation for sampling the output of each D / A converter with the source driver shown in FIG. Timing car art to show.

* Explanation of symbols for the main parts of the drawings

4 scan driver 3a shift register

3c: Sample and Hold 5: Source Driver

9: line memory 9a: amplification circuit

41: buffer 46b: latch

50: write address 51: read address

113: data string conversion circuit 122: address bus switching

123: address generator 127: polarity conversion

141: control circuit 151: analog sample and hold circuit.

The present invention relates to an apparatus and method for driving a liquid crystal panel, and more particularly, to an apparatus and method for driving an active matrix display type color liquid crystal display panel using a low speed block signal. More specifically, the present invention relates to a configuration and driving method of a line memory circuit for driving a liquid crystal panel for adding a color signal to a series of signal actives included in the liquid crystal panel according to a high speed line sequential method.

Since display elements using liquid crystals can be driven at low voltages, they are used for applications requiring low power consumption and the like. One such use is a liquid crystal panel in which images are displayed by arranging liquid crystals in a matrix and applying and driving a video signal sequentially to each liquid crystal.

1A to 1C schematically show a configuration of a conventional active matrix display type color liquid crystal panel.

Referring to FIG. 1A, the panel (active matrix display type color liquid crystal panel) has pixels P ₁₁ , P ₁₂ ,... On a matrix of K, M rows and N columns. P _{1 (N-1)} , P _1N ,... P _{M (N-1)} and P _MN (in which the pixels are collectively referred to as reference part P) are arranged to form a display screen (hereinafter referred to as a screen) 2. Thin film transistors (hereinafter referred to as TFTs), not shown, are provided for each pixel P in one-to-one correspondence.

As shown in FIG. 1B, the pixel P is composed of TFT, Tr and capacitor CA and liquid crystal display LE. In TFT and Tr, a gate is connected to the scan line (gate line) 1 _x and a source is connected to the source line 1 _y . The capacitor CA accumulates a signal transmitted from the source line 1 _y via the TFT and Tr. The color filter which is not shown in figure is arrange | positioned on liquid crystal element LE, and a desired color display is obtained through this color filter in the transmission / blocking state of liquid crystal element LE.

The gates of the TFTs in each row are corresponding scan lines (gate lines) 1 _X 1, 1 _{X 2} , 1 _X 3 _,. 1 Connect to _XM . The scan driver 4 scans the scan line 1 _X1 ... 1 Activate _XM in sequence. In this way, scanning in the vertical direction of the screen 2 is performed.

The source of the TFT of each column is corresponding source line 1 _y1 , 1 _y2,. 1 _y N _k lasts. A color signal is transmitted from the source driver 3 (see FIG. C) to each of the source lines 1 _y1 to 1 _yN . The plurality of pixels P commonly connected to one source line 1 _y are pixel films b ₁ , r ₂ , g ₃ , b ₄ ,... r _(n-1) , g _N (use the reference part Y to refer to the pixel row generically). Here, the symbols b, r, and g denote pixels of colors corresponding to the color video signals B (blue), R (red), and G (green), respectively. Denotes a 2nd order.

In addition, references section 1 _x halttaeneun collectively the scan line in the following description, it will write a reference portion 1 _y halttaeneun collectively to a source line.

Referring to FIG. 1C, a source driving circuit (hereinafter referred to as a source driver) 3 includes a shift register 3a having output terminals Q ₁ to Q _N corresponding to the number N of source lines 1 _y , and an output terminal. is composed of Q ₁ to Q _N one-to-one correspondence with the switching elements S ₁ to S _N analog switch (3b) and the analog sample-and-hold circuit (3c) with the installed. The shift register 3a shifts the output in the direction from the output terminal Q ₁ to Q _N in response to the clock pulse CK, and turns ON the switching elements S ₁ to S _N one by one in the direction indicated by the arrow portion y. And hold the color video signals B, R, and G connected to the switching elements S ₁ to S _N , and individually output to the corresponding pixel type y via the source line 1 _y in the next horizontal period, The color signals B, R, and G of the horizontal period are inserted in parallel.

However, in the above-described configuration, the number of pixels of the screen 2 is increased due to the enlargement and the high quality of the panel 1, and when the high-speed scanning is required and the frequency of the clock pulse CK increases, the linearity of the analog sample hold circuit 3c is increased. It becomes worse and the correspondence becomes difficult because power consumption increases. Therefore, in order to make high-speed scanning possible with a low-speed source driver, and to achieve a small size of the drive circuit, the block is divided into blocks of the screen 2, and the blocks of the plurality of divided pixels are driven by corresponding source drivers, respectively. A method is proposed.

2 is a block diagram showing the electrical configuration of a conventional liquid crystal drive circuit. The liquid crystal drive circuit 21 includes a plurality of line memory circuits 9 for supplying the color video signals R, G, and B to each of the plurality of source drivers 5 to 8 arranged on the main surface portion of the screen 2. To (14). The line memory circuits 9 to 14 will be described later, and all of them include an A / D converter, a memory, a multiplexer, a latch circuit, a D / A converter, and the like.

The screen 2 is constructed in accordance with a multi-matrix scheme. That is, the source line 1 _y is alternately the upper and lower source driver 5, 7; 6,8, and the pixel row y is divided into two halves (driven by the source driver 5 and 6) and the second half (driven by the source driver 7, 8) in the horizontal direction. ) Is composed of four parts, that is, parts K corresponding to each of pixel rows y ₁ to y ₄ .

In the periphery of the screen 2, a plurality of drivers 5 to 8 are disposed corresponding to the divided pixel rows 1 _y to y ₄ . The color video signals R, G, and B respectively input through the lines 1 ₁ , 1 ₂ , and 1 ₃ are respectively used for analog digital conversion, data recording, in the six line memory circuits 9 to 14, respectively. Each is processed in a series of operations of read, latch, and D / A conversion, and then supplied in accordance with alternating signals operations of the source drivers 5-8.

However, in the liquid crystal drive circuit 21 described above, six line memories are required, two for each of the colors R, G, and B of the color signal. In addition, the circuit configuration per line memory includes an amplifier circuit 9a for input color signals (e.g., B), an A / D converter 9d for digitally converting input color signals, as shown in the block diagram of FIG. The buffer circuit 9c, the memory 9d for storing digital data from the buffer circuit 9c, the write address generation circuit 9c for generating the write / read address for the memory 9d, and the read address generation circuit 9f. ), The address multiplex 9h and the readout of the memory 9d which give a write address or a read address to the memory 9d in accordance with the switch / read operation of the memory 9d at a predetermined timing or in accordance with the switched operation. A latch circuit 9i for latching data, a D / A converter 9j for converting latched digital data to an analog signal, and a buffer 9K interposed between the source driver and the D / A converter 9j are required. do. The switching of the write / read operation of the memory 9d is performed via the address multiplexer under the control of the line memory control circuit 9g. In addition, operation control (address generation timing, etc.) of the write address generation circuit 9o and the read address generation circuit 9f is performed by the line memory control circuit 9g.

In addition to the line memory circuits 9 to 14, which are a collection of these various circuits, the order of the input of the color signals B, R, and G to the line memory circuits 9 to 14, and the color order of the pixel y set in the screen 2 (color filter arrangement). ) b, r, g,... There is also a need for a delay circuit and the like not shown for eliminating the inconsistency with and for position converting the data read out from the memory 9d in the arrangement order of the pixel columns. That is, even in the multi-matrix system, each of the source drivers 5 to 8 has the same configuration as that shown in FIG. 1C, and in turn holds one color signal in response to the clock signal CK. On the other hand, each of the line memories 9 to 14 transmits signals to two source drivers. In one line memory, the signal to the source driver 5 or 6 in the switching section and the signal to the source driver 7 or 8 in the latter half are alternately read out, which is output from each of the line memories 9 to 14. It is necessary to match the order in which signals are input to the source drivers 5 to 8 with the color order of the pixel rows y, and a delay circuit or the like is required at each output portion of the line memories 9 to 14. Therefore, each of the source drivers 5 to 8 only drives one quarter row (160 rows in the figure) of the screen 2. Therefore, each of the line memories 9 to 14 can drive the liquid crystal panel at an operating speed of 1/2 for each color and 1/4 for the source drivers 5 to 8 respectively. The disadvantage is that the configuration becomes large and complicated.

An object of the present invention is to provide a liquid crystal drive device having excellent linearity with a simple circuit configuration.

Another object of the present invention is to provide a circuit for driving a multi-matrix liquid crystal panel that does not require a high speed clock signal.

It is still another object of the present invention to provide a circuit for driving low power consumption in accordance with a low speed clock signal of a liquid crystal panel of a high-speed sequential system having a color filter in a delta arrangement.

It is still another object of the present invention to provide a method for driving a multi-matrix liquid crystal panel with low power consumption in response to a low speed clock signal.

It is still another object of the present invention to provide a method of driving a multi-matrix liquid crystal panel having a delta array of color filters using a low speed clock signal.

A circuit for driving a color liquid crystal display panel according to the present invention includes a plurality of driving means for driving a source line, and color video signals R, G, and B to be displayed, respectively, in order of the electric driving means required. And a plurality of first storage means for outputting the video signals R, G, and B.

Each of the first storage means includes a plurality of analog / digital converters for analog-to-digital converting a video signal of one horizontal period for each color, and switching means for outputting the digitally converted data in recording order, and the digital conversion. At least one pair of second storage means for storing and outputting the data, and dividing the data within the one horizontal period into the first half and the second half at the center thereof, and the first half data and the second half data divided by the second memory means. And a plurality of latch circuits for alternately reading data, a plurality of latch circuits for latching the data read by the data reading means, and a digital / analog converter for digitally / analog converting the data output from the latch circuit.

According to another aspect of the present invention, a liquid crystal panel driving line memory circuit includes a second gate paired with a first gate line (scan line) and a first gate line (scan line) in a video signal of one horizontal period. Means for deriving two kinds of video signals in parallel for the line and the two kinds of derived video signals in the first gate line, the second gate line, and the first and second gate lines, respectively. Means for dividing the source line into at least eight groups of odd source lines, even source lines, first half source lines, and second half source lines.

The line memory circuit also reads alternately the pixel data to be transmitted to the first source line and the pixel data to be transferred to the second source line with respect to the first gate line in this storage means. Means for reading the pixel data in the same order as the first gate line with respect to the second gate line after the related reading is finished, and the pixel data imparted by the reading means to at least two groups of the first half and the second half of the decimal line. Means for alternately transferring the corresponding source driver to the correspondingly installed source driver, and signal lines arranged so as not to cross each other for transferring the source driver output to the source line of the liquid crystal panel.

In the liquid crystal drive circuit according to the present invention, in the first storage means, the color video signals R, G, and B in one horizontal period are converted into digital data by an analog / digital converter. The converted digital data is collectively stored in one of the second storage means paired in the recording order by the switching means.

At this time, the contents stored in the other second storage means in one horizontal period at the same time are divided into the first half and the second half of the horizontal period by the data reading means, and are read alternately. The read data is converted into color video signals R, G, and B which are analog signals by a digital / analog converter, and input to the corresponding driving means, respectively. The plurality of driving means drives the liquid crystal element while suitably holding the data of the first half and the second half alternately output.

Further, in the line memory circuit according to another aspect of the present invention, two types of signals are simultaneously derived in parallel for the first line and the second line of the gate line (scan line) from the video signal of one horizontal period. The two kinds of video signal data are recorded in the storage means. When the video signal data corresponding to one gate line is read out from this storage means and applied to the source driver which is the pixel drive means in this half horizontal period, Drive of the liquid crystal panel is enabled.

When reading the pixel data from the storage means, the corresponding video signal data of one gate line is alternately read in the first half and the second half of the source line, and then alternately read to the source driver for driving the first half and the second half of the source line. It is possible to supply a signal, which makes it possible to suppress the clock frequency that defines the operation speed of the source driver by 1/2, and to operate the source driver at the same clock frequency as in the conventional method even in a high-speed sequential method. The linear characteristic of the source driver is improved and power consumption is reduced.

In the delta-array color filter, there are 1.5 pixel positional deviations between the superior gate line and the odd gate line. However, this deviation shifts the sampling clock phase by 1.5 clocks when converting the analog video signal into a digital signal. We can cope with it.

4 schematically shows an electrical configuration of a liquid crystal drive circuit as an embodiment of this invention.

Referring to FIG. 4, the liquid crystal driving circuit 31 is divided into four configurations as an example, and sources the source drivers 33, 34, 35, and 36 for driving the display panel 32. A pair of line memory circuits 37 and 38 for supplying the color video signals R, G, and B to the drivers 33 to 36 are provided.

The source drivers 33 to 36 are disposed on the upper left, upper right, lower left and lower right of the periphery of the display panel 32, respectively.

The line memory circuit 37 supplies the color video signals R, G and B to the source drivers 33 and 35, while the line memory circuit 38 supplies the color video signals R, G and B to the source driver ( 34) and (36).

Unlike the related art, the liquid crystal drive circuit 31 is configured by using only two memory circuits 37 and 38.

In FIG. 4, the case where the number of pixel columns (source lines) of the display panel (hereinafter referred to as panel only) 32 in the horizontal direction of the screen (horizontal direction of the drawing) is 640 is shown as an example. Since each of the 640 pixels is driven by a pair of line memory circuits 37 and 38, the number of pixel columns for each line memory circuit is 320. The panel 32 is configured in a multi matrix manner as shown in FIG.

The first source driver 33 on the left side and the third source driver 35 on the right side are commonly connected to the output lines y _1b , y _1r , and y _1g of the first line memory circuit 37. . As an example, the four source drivers 33 to 36 have an upper left first source driver 33 of 0 ^j , a lower left second source driver 34 of 90 °, and an upper right third source driver 35. The clock signal of phase 180 degrees is given, and the right side 4th source driver 36 is 270 degrees. Thus, the source drivers 33 to 36 are cyclically activated in the order of top left to bottom left to top right and bottom, and receive video signals B, G and R from the corresponding line memory circuits 37 and 38.

The panel 32 has color filters (not shown) on the left side of the screen. It is set in advance as follows. Therefore, pixel row y is also (b1), (r2), (g3) (b4),... The arrangement of colors is determined as (g ₆₃₈ ), (r ₆₃₇ ), (b ₆₄₀ ). The 640 pixel columns b ₁ to b ₆₄₀ are divided into two at the center of the screen and included in the first half of the horizontal scanning period of the screen, and the pixel columns b ₁ , r ₂ , g ₃ ,. The first source driver 33 and the second source driver 34 on the left side of the screen drive each other (b ₃₁₉ ) and (g ₃₂₀ ), and the pixel columns r ₃₂₁ , (b ₃₂₂ ), ( g ₃₂₃ ),... (r ₆₃₉ ) and (b ₆₄₀ ) are alternately driven by the third source driver 35 and the fourth source driver 36 on the right side of the screen.

The pair of line memory circuits 37 and 38 for supplying the color video signals R, G, and B to the first to fourth source drivers 33 to 36 may include a sequence of signals connected to a corresponding source driver, The clock phase for activation is only different and the operation is the same. Coloring of the three colors of the color video signals R, B, and G of the first to fourth source drivers 33 to 36 is delayed by one clock and is repeated in three clocks. The drive circuit 31a shown surrounded by a broken line in FIG. 4 composed of the first line memory circuit 37 and the first source driver 33 and the third source driver 35 disposed above the screen is shown. The operation of the embodiment will be described below.

Supply order of respective signals R, G, and B in the first line memory circuit 37 to the first source driver 33 and the third source driver 35 on the upper side of the screen included in the driver circuit 31a. That is, the reading order must be the same as the color order of the pixel row y determined by the color filter as described above. Therefore, as shown in the figure, color signals are supplied in order of B-R-G ... to the first source driver 33 on the left side, and R-G-B-R ... in order of the third source driver 35 on the right side. On the other hand, the order in which the first line memory 37 inputs the color video signals R, G, and B is in the same order of BRG ... as the first driver 33, which will be described later. The recording of the color signal to (37) is performed.

5 is a block diagram showing the electrical configuration of the line memory circuit 37 of the present embodiment. The first line memory 37 and the second line memory circuit 38 shown in FIG. 4 have the same configuration. Hereinafter, the first line memory circuit 37 will be representatively described. In addition, the symbols b, r, and g added to the reference numerals correspond to the color signals B, R, and G, and when referred to generically, the symbols b, r, and g are omitted and are represented by reference numerals only.

No. (hereinafter referred to, A / D) 1 the line memory circuit 37 is a color video signal inputted via the not shown line amplifier B, R, no log / Digital to the G transform each digital converter (39 _b), (39 _r), (39 _g) and the a / D converter (39 _b), (39 _r), (39 _g) and the a / D converter memory to be described later for the digital data of each color derived from the 39 Three state buffers 40b, 40r, and 40g whose ON / OFF are controlled in accordance with the recording order of the furnace are included. The line memory circuit 37 further includes three state buffers 41 and 42 for adding the write data derived from the three state buffers 40 to the pair of memories 43 and 44 at the time of writing. And the color signals Bd, Rd, and Gd of the memory on the read side of the pair of memories 43 and 44, which are recording / reading materials, for deriving the data latch circuit 46 of the next step. A data multiplexer 45.

In addition, the line memory circuit 37 further reads the data of the color signals output from the data multiplex 45 and latches them in order, and the data latch circuits 46 (b), 46r, 46 (g). ) And digital / analog (hereinafter referred to as D / A) converters 47b, 47r, and 47g for converting the data latched by the data latch circuit 46 into analog signals, respectively. Amplifiers 48b, 48r, 48g for amplifying the levels of the converted color signals B, R, and G and outputting them to the source driver (see Fig. 4), and the electric memories 43, 44 at predetermined timings. ), And an address multiplex 49 for selectively indicating an address.

The line memory circuit 37 further includes a write address generation circuit 50 for generating a write address at the time of data writing (write cycle), and a read address generation circuit for generating the address of the memory to be read at the time of data reading (read cycle) ( 51 and a line memory control circuit 52 for controlling the operation of these circuit blocks.

Next, the operation of the line memory circuit 37 will be described. The number of horizontal pixels in charge of the line memory circuit 37 is N. In one memory 43 or 44, digital data corresponding to one pixel is recorded. On the other hand, the line memory circuit 37 supplies the color video signal to both the source driver 33 in the first half and the source driver 35 in the second half. If the memory area of one memory 43 or 44 corresponds to one pixel, it is necessary to divide the memory area into the first half and the second half. The boundary address between this first half and second half is

N/22 ^x

N / 2

In other words,

logz(N/2)X

logz (N / 2)

Obtained by Assume this value X is a transition bit. The write address generation circuit 50 sets the write address A ₁ for writing the digital data in the first half (H / 2) period of one horizontal period (H / 2) in accordance with this switching bit, so that the write address A ₁ is 0.1, ... j (KKL, jLz). ^x ), and on the other hand, a write address A ₂ for recording digital data of the second half (H / 2) is generated in the order of 2 ^x +0, 2 ^x +, ... 2 ^x + j. Thus, in the area A ₁ of addresses 0 to j <2 ^x of the memory 43 or 44, two data to be transmitted to the first source driver 31 are recorded, while a memory of address 2 ^x or more is recorded. In the area A ₂ , data to be supplied to the second source driver 35 is recorded. This is when the address (x + 1) bits referred to when readily area A ₁ and the area A ₂ of the most significant bit to a "0", the second half of the address area (A ₂₎ "1" about the about the address areas A ₁ of the first part You can switch.

Now, let N = 320 because the pixel row y includes 640 pixel columns. At this time, x = 8. Therefore, the data of the 320 color signals B, R, and G of the first one horizontal period H ₁ is used in the first half of one pair of memories 43, 44, for example, the address of the memory 43. The latter half of A ₁ ) (0 to j: j + 159) is written to the address A ₂ (2 ⁸ to 2 ⁸ + j) of the memory 43. The writing is performed in accordance with the write address generated by the write address generation circuit 50 under the control of the line memory control circuit 52.

In the next one horizontal period H ₂ , the read / write operations of the memory 43 and 44 are switched, and the data is written to the addresses A ₁ and A ₂ of the other memory 44. In addition, the data written into the memory 43 in the one horizontal period H ₁ preceding it is read out based on the read address designated by the read address generating circuit 51. This address generation and switching of operation are performed by the line memory control circuit 52.

That is, the line memory control circuit 52 alternately switches the read / write operations of the pair of memories 43 and 44 every one horizontal period H, and also generates the write address generation circuit 50 and the read address. The address generating circuits 50 and 51 and the multiplexer are configured to generate a write address and a read address while alternately switching the first and second switching bits X (where X = 8 in this embodiment) with respect to the circuit 51. Control 49.

Therefore, the reading of data is performed in one horizontal period H _x, where the address is 0,2 ⁸ , 1,2 ⁸ +1 in the memory (for example, the memory 43) in which data is written in the horizontal period H _x-1 before that one. In the next one horizontal period, H _{x + 1,} two pairs of memory 43 and 44 are read out alternately, such as, 2, ..., and the address is 0,2 ⁸ , 1,2 ^8. Front and rear data are alternately read out, such as +1, ... The same applies to the recording of data.

In this way, in the present invention, when the read / write operations of the memory 43 and 44 are switched every one horizontal period H, and data is being read from one memory, the data is written into the other memory. In addition, one horizontal period H is divided into front and rear halves, and alternately the recording / reading into the first half and the second half is performed. In this configuration, the electrical configuration of the liquid crystal drive circuit 31 is simplified and the operation is speeded up.

In order to realize the above-described operation, in the first line memory circuit 37, the three-state write buffers 41 and 42 are respectively arranged on the write input side of the pair of memories 43 and 44 on the read output side. 45 is provided, and writing / reading of data is controlled by the line memory control circuit 52. As shown in FIG.

For example, when the memory 43 is a write (write cycle) and the memory 44 is in a read (read cycle) state in one horizontal period H ₁ , the second write connected to the second data line 1 ₂ is performed. derived by the buffer 42 is oN, a / D converting the color video signal B, R, the data lines ₍₁₂₎ the digital data of G is recorded by the memory 43. On the other hand, the second input terminal (a2) of the data multiplexer 45 is a high impedance with respect to the data line _(12), the input of the digital data is inhibited.

On the other hand, the first write buffer 41 connected to the first data line 1 ₂ has a high impedance, and the first input terminal a1 of the data multiplexer 45 is turned ON, and the data line 1 ₁ is turned on. Digital data in the A / D conversion circuit 39 is not derived. Instead, the data is a first data line ₍₁₁₎ obtained is, data multiplexer 45 to via a latch circuit (46 (b)) of the next-stage data to, (46r), (46 read out from the memory 44 ( g)).

In the next one horizontal period H ₂ , the read / write cycles of the memories 43 and 44 are reversed to read the memory 43 and write the memory 44. In this case, the first write buffer 41 and the second input terminal a2 of the data multiplexer are turned on, and the output of the second write buffer 42 and the first input terminal a1 of the data multiplexer 45 become high impedance. . Digital data in the A / D converter 39 is derived via the first data line 1 ₂ and recorded in the memory 44. In this case, the first write buffer 41 and the second input terminal a2 of the data multiplexer are turned on, and the output of the second write buffer 42 and the first input terminal a1 of the data multiplexer 45 are high impedance. do. The digital data in the A / D converter 39 is derived via the first data line 1 ₂ and written in the memory 44. On the other hand, data is read from the memory 43, and the data latch circuits 46 (b), 46r, 46 (g) of the next stage are passed through the data multiplexer 45 on the second data line 1 ₂ . ) Is entered. In this manner, digital data signals B, R, and G of the digital data are alternately recorded and read out.

A / D converters 39b, 39r, 39g and D / A converters 46 (b) used in the line memory circuit 37 (the same applies to the line memory circuit 38 in FIG. 4). , 46r, 46 (g) perform data conversion in synchronization with the clock signal? C provided to the line memory control circuit 52. The A / D converters 39b, 39r, and 39g convert analog color video signals B, R, and G into digital data for output, and the D / A converters 47b, 47r, and 47g. Is output from the latch circuits 46 (b), 46r, 46 (g), and converts the digital data of the color video signals B, R, and G into an analog signal to convert the lines 1 ₁ b, (1). _{To 1} r), (1 ₁ g)

Each of the color signals B, R, and G is A / D converted into the A / D conversion circuits 39b, 39r, and 39g in parallel at the same time. ), 40r, and 40g are turned into a conductive state (enable) one by one, and digital data is output one by one and recorded in the memory 43 or the memory 44. Further, the digital data read out from the memory 43 or 44 and then passed through the data multiplexer 45 is input in parallel to the data latch circuits 46 (b), 46r, 46 (g). The latch pulses are divided into three colors by the latch pulses provided at timings in accordance with the reading order.

In the case of one color, since data is latched at a rate of one to three clocks, three clocks are subjected to D / A conversion of the same data, which results in three times oversampling. This three times oversampling allows the sampling clock frequency band to be outside the video signal frequency band, and the respective front end and D / A converters 47 of the A / D converters 39, 39b, 39r, and 39g. It becomes easy to design a sampling clock interference cancellation filter that matches a video signal amplifier (not shown) connected to the next stages of (47b), (47r), and (47g), respectively.

The color video signals B, R, and G are applied to the first source driver 33 and the third source driver 35 arranged by the left and right in the liquid crystal drive circuit 31a on the upper side of the screen 32 shown in FIG. The order of supply is the same as the color order set by the color filter (not shown) disposed on the screen as described above, so that the first source driver 33 on the left side of the screen is in the order of BRG, and the second source driver ( 35 is in the order of RGB.

On the other hand, the order in which the line memory circuit 37 inputs the color video signals R, G, and B is the same as that of the BRG, which is in the order of writing to the memory 43 or 44. However, the order of outputting the received color video signal to the pixel row y (i.e., source drivers 33 and 35) is the first source driver 33 in the first half and the source driver 35 in the second half as shown in FIG. Alternating data output causes b ₁ -r ₃₂₁ -r ₃ -g ₃₂₃ -g ₅ -b ₃₂₅ -b ₇ . Becomes In this case, since the color video signals of the same color in the second half and the first half need to be continuously output from the line memory circuit 37, there is no time for switching of the color video signals.

Therefore, if the reading order is reversed in the first half, and data reading is performed alternately in the order of the second source driver 35 to the first source driver 33, the data reading order is r ₃₂₁ -b ₁ -g ₃₂₃ -r _3- b _325- g ₅ ..., each of the source drivers 33 and 35 can have the same color at equal intervals, and in addition, the color video signal in the line memory circuit 37 is BRG. Into the first memory 43 and the second memory in the order of, while in the first memory 43 and the second memory 44, R (second half) -B (first half) -G (second half) -R ( Reads to be 1) -B (2nd half) -G (1st half) ... and outputs the color video signals B, R, and G in the order required by the first source driver 33 and the second source driver 35. do.

6 and 7 are time charts showing the operation of the line memory circuit of this embodiment. As described above, in the present embodiment, the screen 2 is divided up and down, and the upper side is controlled by the first line memory circuit 37 and the lower side is controlled by the second line memory circuit 38. The order in which the and driver drivers differ is only different, the operation shows timing, and in Fig. 7, the write operation is shown.

_c의 타이밍을 나타내며 제6b도는 제1과 제3소스 드라이버(33,35)에 인가된 소스 드라이버 클럭 신호의 타이밍을 나타내다.6A shows a clock signal applied to the first line memory circuit 37.

The timing of _c and FIG. 6b show the timing of the source driver clock signals applied to the first and third source drivers 33 and 35.

FIG. 6C is a waveform of the read address signal output from the read address generation circuit 51 shown in FIG. As described above, in the present embodiment, the data of the color video signals R, G, and B in one horizontal period is divided into the first half and the second half, and the second half data in the memory 43 or 44 is (2 ⁸ ), that is, 256. Since the first half data is stored at address 0, the read address generation circuit 51 alternately outputs the addresses in which the first half data and the second half data are stored.

_G)의 1 펄스마다에 칼러 비디오 신호R, G, B 각 색에 대응한 데이터 래치 신호

_R,

_G,

_B가 라인 메모리 제어 회로(52)에서 데이터 래치 회로(46(b)),(46r),(46(g))에 따로따로 부여된다. 이 래치 펄스에 응답해서 제6c도에 도시되는 판독 어드레스 신호로 판독된 데이터가 대응하는 데이터 래치 회로(46)에 의해서 래치된다. 그때, 제4도에 도시되는 화면(2)의 후반의 최초의 화소열 r₃₂₁이 칼러 비디오 신호 R(256)에 상당하며, 전반의 최초의 화소열(b₁)이 칼러 비디오 신호(0)에 상당함으로 데이터 래치 신호

_B,

_R,

_G는 B데이타 래치

_B-R 데이터 래치

_R-G 데이차 래치

_G의 차례로 출력된다. 제6(d), f, h도는 이같이 해서 출력되는 각색에 대응한 데이터 래치 신호의 타이밍을 도시한다.The reading of the data is performed by using a clock signal (

Data latch signal corresponding to each color video signal R, G, and B for each pulse of _G )

_R ,

_G ,

_B is separately provided to the data latch circuits 46 (b), 46r, 46 (g) in the line memory control circuit 52. In response to this latch pulse, the data read by the read address signal shown in FIG. 6C is latched by the corresponding data latch circuit 46. At that time, the first pixel column r ₃₂₁ of the second half of the screen 2 shown in FIG. 4 corresponds to the color video signal R 256, and the first pixel column b ₁ of the first half is the color video signal 0. Equivalent to the data latch signal

_B ,

_R ,

_G is B data latch

_B -R data latch

_R -G Day Latch

_It is output in order of _G. The sixth (d), f, and h diagrams show the timings of the data latch signals corresponding to the respective colors output in this manner.

_B)에 의해서 칼러 비디오 신호 B의 데이터가 순차적으로 래치되는 타이밍을 나타내며, 제6(g)도는 마찬가지로 해서 칼러 비디오 신호 R의 데이터가 순차적으로 래치되는 타이밍을 나타내며, 제6k도는 마찬가지로 해서 칼러 비디오 신호 G의 데이터가 순차적으로 래치되는 타이밍을 나타낸다. 이들 각색의 데이터를 래치하기 위한 래치 신호

_B,

_R,

_G는 제6a도에 도시되는 클록 신호

_C의 3클록으로 일순회하며, 3클록에 1회의 비율로 데이터가 래치 회로(46(b)),(46r),(46(g))에 래치된다.6E shows the B data latch signal (

_B ) shows the timing at which the data of the color video signal B is sequentially latched. FIG. 6 (g) also shows the timing at which the data of the color video signal R is sequentially latched, and FIG. 6k is similarly the color video signal. The timing at which the data of G is sequentially latched is shown. Latch signal for latching these various data

_B ,

_R ,

_G is the clock signal shown in FIG. 6A

One cycle of three clocks of _C is performed, and data is latched to the latch circuits 46 (b), 46r, and 46 (g) at a ratio of one to three clocks.

_C의 타이밍으로 차례로 제1소스 드라이버(33) 및 제2소스 드라이버(35)에 들여져서 샘플에 홀드된다. 이런 다음, 소정의 타이밍 예컨대, 수평 동기 신호의 타이밍으로 소스 드라이버(33),(35)에서 소스 라인상으로 각 색 신호가 전달되며, 활성화된 주사 라인(게이트 라인) 1_x에 접속되는 화소 P가 발생한다.The latched data is given to the next stage D / A converters 47b, 47r, and 47g, which are then converted into analog signals, and then the source driver clock.

The first source driver 33 and the second source driver 35 are sequentially held at the timing of _C and held in the sample. This then, a predetermined timing, for example, at a timing of the source driver 33, 35 of the horizontal synchronizing signal to the source lines, each color signal is transmitted, the active scan lines (gate lines), a pixel which is connected to the 1 _x P Occurs.

_C)의 타이밍에 동기해서 각 A/D변환기(30b),(39r),(39g)는 화소의 배열순(색 순서)와 동일 순서로 칼러 비디오 신호 R, G, B를 각각 디지틀 데이터로 변환한다. 제7(b),c,d도는 각 색의 디지틀 변환된 데이터가 출력되는 타이밍을 나타낸다. 시각(t₀)는 1수평 기간이 시작되는 타이밍이다.FIG. 7A shows the timing of the clock signal? _{C applied} to the first line memory circuit 37 in the same manner as in FIG. 6A. This clock signal (

_In synchronization with the timing of _C ), each of the A / D converters 30b, 39r, and 39g converts the color video signals R, G, and B into digital data in the same order as the pixel arrangement order (color order). do. 7 (b), c, and d show timings at which digitally converted data of each color is output. The time t ₀ is the timing at which one horizontal period begins.

_C에 동기해서 각 색의 기록 신호 1_B,1_R1_G를 출력한다. 제7(f)도의 데이터 기록 신호 1_B에 의해서 3 스테이트 버퍼(40b)는 제7(g)도로 도시되듯이 A/D변환기(39b)에 의해서 디지틀 변환된 컬러 비디오 신호 B의 데이터를 출력한다. 제7h도의 R 데이터 기록 신호 1_R에 의해서 3 스테이트 버퍼(40r)는 제7(i)도로 도시하듯이 A/D 변환기(39r)에 의해서 디지틀 변환된 칼러 비디오 신호 R의 데이터를 출력한다. 제7(j)도에 도시되는 칼러 비디오 신호 G의 데이터를 출력에 대해서도 마찬가지이다. 각 데이터 기록 신호 1_B,1_R,1_G는 3 클럭(

_C)를 주기로 발생되며 칼러 비디오 신호 R, G, B를 차례로 기록하는 타이밍을 부여함으로 각 색이 데이터는 제71도에 도시되듯이 1수평 기간의 개시와 동시에 메모리(43) 또는 메모리(44)의 선두 번지로부터 칼러 비디오 신호 B-R-G-B…의 차례로 순차 기록되어져 간다.FIG. 7E shows the timing of the write address signal output from the write address circuit 50. FIG. The address multiplexer 49 has a clock signal as shown in Fig. 7f, h, i.

_In synchronization with _C , the recording signals 1 _B and 1 _R 1 _G of each color are output. Claim 7 (f) a separate data recording signal 1 in by 3-state buffer (40b) _B outputs the data of the 7 (g) road the digital conversion by the A / D converter (39b) shown Just as color video signals B . The degree R 7h data recording signal by 1 _R 3-state buffer (40r), and outputs the data of the 7 (i) as shown roads A / D converter (39r) the converted digital color video signal R by the. The same applies to the output of the data of the color video signal G shown in FIG. 7 (j). Each data recording signal 1 _B , 1 _R , 1 _G is 3 clocks (

_C ) is generated in cycles, and the timing of recording the color video signals R, G, and B in sequence is given so that the data of each color is shown in FIG. 71 at the same time as the start of one horizontal period. Video signal from the leading address of BRGB… Are recorded sequentially.

_S로 동작할 수 있다. 또, 라인 메모리 회로(37),(38)가 1쌍 설치되어 있을 뿐이며, 각 라인 메모리 회로(37),(38)에 있어서 각 색 신호는 라인 메모리 클록

_C의 1/3의 속도로 데이터의 래치, 출력이 행해지고 있으므로 저속 동작의 소스 드라이버로 액정 패널을 고속 구동하는 것이 가능해진다. 또, 라인 메모리 회로 1쌍 설치되고 있을 뿐이며, 하나의 라인 메모리 회로가 3색을 처리할 수 있으므로 소형, 간단한 구성으로 염가인 액정 구동 회로를 가질 수 있다.In the above configuration, the source drivers 33 to 36 are the source driver 33, the source driver 34, and the source driver 35. Since the source drivers 36 are activated in sequence, each source driver 33 to 36 has a low speed clock signal.

_{Can work with S} Moreover, only one pair of line memory circuits 37 and 38 are provided, and each color signal in each line memory circuit 37 and 38 is a line memory clock.

_Since data is latched and output at a speed of 1/3 of _C , the liquid crystal panel can be driven at high speed by a source driver of a low speed operation. Moreover, only a pair of line memory circuits are provided, and since one line memory circuit can process three colors, it can have a cheap liquid crystal drive circuit with a compact and simple structure.

In the above configuration, the arrangement of colors is the same as that of the respective scanning lines (gate lines), and the color filters (pixels) are assumed to be arranged in a matrix of rows and columns. The scanning order of the scanning lines (gate lines) is not specifically described as being interlaced or interlaced. In the above-described configuration, this scanning order is assumed to be the scanning driver 4 (see also FIG. 1A), so that the configuration of the line memory circuits 37, 38 is also applicable in this manner.

However, when the color filter is eight arrays, it is necessary to consider the timing of reading the data and the like according to the scanning method of the scanning line. This point is explained.

In general, it is necessary to perform AC drive in order to operate the liquid crystal. For this reason, inverting the polarity of the signal applied to the liquid crystal at a predetermined fixed period is performed. In other words, when driving a liquid crystal panel, scanning of gate lines (signal lines for selecting a row to which one liquid crystal element is connected in a liquid crystal panel; a scanning line) is performed in sequence and scanning all gate lines in one field. In this case, a configuration in which the polarity of the video signal is reversed every horizontal period in accordance with the scanning of the gate line is taken. If the number of gate lines is large and all the gate lines cannot be scanned within one field period, a method for scanning all the gate lines within this predetermined one field period is conventionally known as a double speed sequential method and an interlace method. The method is performed.

In the double-speed sequential method, as shown in FIG. 8, scanning is performed by pairing two gate lines, and the pair of gate lines is replaced for each field. In field A, gate lines g ₁ and g ₂ are paired and simultaneously scanned, and gate lines g ₃ and g ₄ are simultaneously paired and scanned. Hereinafter, the gate lines g ₅ and g ₆ are similarly scanned in pairs, and the gate lines g ₇ and g ₈ are scanned in pairs. At this time, a positive signal is applied to each liquid crystal to the gate lines g ₁ and g ₂ , and a negative signal is applied to the liquid crystals of the gate lines g ₃ and g ₄ , and the gate line g ₅ is applied to the liquid crystals of the gate lines g ₃ and g ₄ . A positive signal is applied to the liquid crystal of (g ₆ ). In the next field 13, the gate lines g ₂ and g ₃ are scanned in pairs, and the gate lines g ₄ and g ₅ are scanned in pairs. In the field B, a negative signal is applied to the liquid crystal pixels of the gate lines g ₂ and g ₃ , and a positive signal is applied to the liquid crystal pixels of the gate lines g ₄ and g ₅ . do. Hereinafter, in the fields (C), (D), and (E), paired gate lines are switched and scanned. In this double-speed sequential method, the signal polarity for the liquid crystal pixels connected to one gate line is switched every two fields (one frame). One horizontal period 1H is a period in which all of the liquid crystal pixels connected to one gate line are being driven, and corresponds to one horizontal period of a normal laser scanning display device. One field is frequency 60H _Z. In this double speed sequential method, all gate lines can be scanned within a period of one field, so the response to moving pictures is excellent.

However, in the above-described double speed sequential method, when the gate lines are paired two by two, that is, the odd gate line and the even gate line are simultaneously scanned, the color filter of the color display liquid crystal panel is in the delta arrangement. Correction cannot be made and horizontal resolution deteriorates.

Here, the delta (δ) array is a color arrangement of color filters in which colors different from each other, that is, color filters of R, G, and B are arranged at respective vertices of arbitrary equilateral triangles of pixels on the liquid crystal panel.

In the interlace method, as shown in FIG. 9, a gate line is scanned by one skip in each field, and a gate line is scanned so that all gate lines are scanned by two fields. That is, in this interlacing method, as shown in FIG. 9, the odd gate lines g ₁ , g ₃ , g ₅ , and g ₇ are scanned in the field A, and the next field B is scanned. Gate lines g ₂ , g ₄ , g ₆ , and g ₈ are scanned. When the color filter of the liquid crystal panel has a delta arrangement and the signal electrodes for applying a signal potential to the liquid crystal are arranged in a zigzag shape, a shift of 1.5 pixels occurs in the odd and even lines of the gate line. For this reason, the odd lines and even lines of the gate lines cannot be driven at the same timing. However, in this interlacing system, only the instrument lines of the gate lines or only the even lines are scanned in each field. When the drive timing is pinned, the delta arrangement of the color filter can be corrected, and the horizontal resolution can be improved.

However, in the interlace method, since only one half of the gate lines of the previous gate line are scanned in one field, the gate lines that are not scanned are updated until the image information given in the previous field is updated by scanning in the next field. It is held. That is, since each liquid crystal pixel holds image information for one frame, the correspondence with moving images is deteriorated.

In addition, in the double-speed sequential method and the interlace method, as shown in FIGS. 8 and 9, since the period of polarity inversion of the signal required for alternatingly driving the liquid crystal is 2 frames, that is, 15H _Z , the flicker The drawback is that it is easy to occur.

The drawbacks of the above-described double-speed sequential method and interlace method, that is, correction of delta arrangement, responsiveness to moving pictures, and generation of flicker can be solved by the high-speed line sequential method. This high-speed sequential method scans two gate lines in one horizontal period. Instead of scanning two gate lines simultaneously, one gate line is scanned for one half of the horizontal period, and the other half horizontal period. It differs from the double speed line sequential method in that the other gate line is scanned and two gate lines are scanned in one horizontal period. That is, as shown in FIG. 10, in this high-speed sequential method, the gate lines g ₁ and g ₂ are selected in pairs, and the gate lines g ₁ are scanned during the first half of the horizontal period. In the remaining horizontal period, the gate line g ₂ is scanned. In this high-speed sequential method, since the gate lines are scanned one by one, the delta arrangement can be corrected. In addition, since two gate lines are scanned in one horizontal period, all gate lines can be scanned within one field period, The response is also faster. In addition, since each gate line is independently scanned, the polarity of the video signal can be reversed at a half horizontal period, i.e., when the scanning of one gate line is completed. With this cycle of polarity inversion of a signal to be required due to AC driving of the liquid crystal can be accelerated by one frame that is 30H _Z, it is possible to improve the flicker of the LCD panel. That is, as shown in FIG. 10, it is possible to invert the signal polarity of the gate line for each of the frames A, B, C, D, and E, and the polarity inversion period of the signal is one frame.

However, this high speed line sequential system needs to drive a liquid crystal panel by supplying a video signal corresponding to a pixel connected to one gate line to a source driver in a 1/2 horizontal period. That is, the source driver cannot supply the given video signal as it is, and processing such as time compression of the video signal of one horizontal period into the video signal of one-half horizontal period is required.

Also, in order to correct the model arrangement of the color filter, since the video signal needs to be shifted by 1.5 pixels for the odd and even lines of the gate line, the two gate lines in the video signal of one gate line are required. Even if a video signal is generated, the two types of video signals cannot be directly supplied to the source driver, and some signal processing is required. In addition, since it is necessary to scan one gate line in a half horizontal period and transfer the signal potential to each liquid crystal pixel, the source driver for transferring this signal potential to each liquid crystal pixel is a conventional line sequential method. And it is necessary to operate at the clock frequency of twice the inter-line system, the degradation of the linear characteristics, the increase of power consumption.

Therefore, in the liquid crystal panel driving line memory circuit according to another embodiment of the present invention, the following configuration is taken.

First, before describing the specific configuration of another embodiment of the present invention, the operation of the line memory circuit for driving the liquid crystal panel according to the present invention will be described in principle. In the liquid crystal panel, when the color filter is a delta array and the signal electrodes of the liquid crystal pixel are arranged in a zigzag pattern in the liquid crystal panel, the arrangement of the pixels is shifted by 1.5 pixels in the odd lines and even lines of the gate lines. Therefore, when analog video (A / D) conversion of a video signal of one horizontal period to derive a video signal for two gate lines, the tie network of the clock giving the A / D operation timing is connected to the odd line of the gate line. It is necessary to shift 1.5 pixels in the even line. In practice, the video signal per pixel of the liquid crystal panel is A / D-converted at one clock, so that the clock given to the A / D converter is shifted by 1.5 clocks from the odd line and even line of the gate line.

The red (R), green (G), and blue (B) signals of the video signal are divided into two lines, one for the odd line of the gate line and one for the even line. At the same time, it is converted to A / D simultaneously.

A 3-state buffer is provided immediately after the A / D converter installed corresponding to the R, G, and B colors of the video signal, and the R, G, and B outputs from the A / D converter are suppressed by suppressing the operation timing of the 3-state buffer. The data output timing is controlled to output video data of R, G, and B in the same arrangement order as that of the color filter arrangement of the liquid crystal panel.

In the above-described operation, video data of one horizontal period is formed for the odd lines of the gate lines. The data column corresponding to the one horizontal period thus formed is divided into the odd lines and even lines of the gate line. Thus, in the case of the configuration in which video data is recorded in two memories of the odd line memory and the even line memory, respectively. The 1/2 horizontal period is a data reading operation in only one memory. The efficiency of memory access is poor, and the video is recorded at half the time required for data writing (time corresponding to one horizontal period). It is necessary to read data from memory. Thus, the data string is converted before the memory video signal data is written so that the memory and the data can be accessed during the data and reading, as in the data recording.

Specifically, the data string divided into the odd lines and even lines of the gate line is redistributed again into the video data corresponding to the odd lines of the source line and the video data corresponding to the even lines of the source line. The video signal supplied to the source driver is a pixel data string in which the video data for the odd lines of the source lines and the even lines of the source lines alternately appear. Therefore, when the above-described data string conversion is performed, data reading from the memory is alternately performed on the video data for odd source lines and the video data for even source lines. By this, a memory for storing video data for odd source lines and a memory for storing video data for even source lines are provided, and data reading from two memories having a configuration for converting the above-described data strings is performed alternately. As a result, the congestion rate of memory access is improved, and data can be read at the same time as the time required for data writing.

If the video signal is not processed continuously, the liquid crystal panel cannot be driven to display an image. For this reason, a pair of a memory for storing the video data for the cardinality of the source line described above, a memory for storing the video data for the excellent source line, and two installed memories are provided, and a recording operation is performed in one pair of memories. If there is, the other pair of memories is configured to perform a read operation, and the write operation and the read operation are alternately switched to two pairs of memory every one horizontal period. With this switching configuration, data is read out in parallel with the write operation in one pair of memories, and the video signal can be processed continuously.

The address at the time of writing the data column to the memory is the number of pixels in one horizontal period (one gate line) so that separation and switching of odd lines and excellent lines of the source lines and the gate lines in the same memory can be easily performed. When the number of liquid crystal pixels connected to N is set to N, the switching bit X for switching between the first half and the second half of the source line is X ≦ log 2 (N / 4), and the odd line and the excellent line of the gate line are The bit y for switching is set to y = x + 1.

In video data after data string conversion, video data for odd lines of data lines are alternately recorded in a corresponding memory. That is, in the data column conversion, for example, data of odd lines of gate lines and even lines of gate lines are alternately recorded with respect to odd source lines. Therefore, in the 1/2 horizontal period, the write addresses are incremented one by one while alternately repeating the reset and the set of bits y for switching the odd and superior lines of the gate line. Thus, in the 1/2 horizontal period, the area where the video data for the odd line of the gate line is written in the memory corresponds to the reset value of the switching bit y, and the video data for the excellent gate line has the switching bit y set. The address is stored in the latter half of the memory.

The switching bits x for switching between the first half and the second half of the source line are reset and set respectively in the first half horizontal period and the second half horizontal period. This makes it possible to make the recording position of the memory different in the half horizontal period in the first half and the half horizontal period in the second half. As a result, the memory space of a pair of memory is divided into regions corresponding to each of the two gate lines, regions corresponding to the first half and the latter half of the odd source lines, regions corresponding to the even source lines, and first half of the even source lines. It is divided into eight regions of regions corresponding to the latter half, and video data corresponding to each of these eight divided regions is recorded.

When the video data is read from the memory, the arrangement of the read data must be in the order of the video signals supplied to the source driver, so that the first and second switching bits x of the source line are reset in half horizontal period. The read address is incremented by one while repeating the set alternately. The switching bit y of the odd line of the gate line and the even line is reset or set depending on the field at that time in the first half horizontal period and the second half horizontal period. That is, in a field, the switching bit y is reset in the first half horizontal period, and the switching bit y is set in the second half horizontal period. In the other field, the switching bit y is set in the first half horizontal period and the switching bit y is reset in the second half horizontal period.

The video data read out from the memory according to the read address described above is a digital signal, while the video signal is applied to the source driver in the form of an analog signal. Therefore, it is necessary to convert the read video data digital analog (D / A), and the digital polarity switching is performed before this D / A conversion.

In the digital polarity switching circuit, the bit value of the data is inverted and non-inverted in accordance with the polarity switching signal, and the polarity of the video signal is switched by performing D / A conversion of the video data passed through the digital polarity switching circuit.

Conventionally, in the configuration of switching the polarity of a video signal, an analog video signal is applied to an inverting amplifier and a non-inverting amplifier, and each amplifier output is switched using an analog switch as a polarity switching signal and outputted. Therefore, in the conventional configuration in which polarity switching is performed in this analog form, an inverting amplifier, a non-inverting amplifier, an analog switch, and a three-point apparatus are required, and the circuit scale becomes large.

On the other hand, in the digital polarity switching circuit of the present embodiment, the bit value of the video data is inverted and the non-inverted can be selectively performed by the switching signal by using an exclusive OR gate, or the like. It is only necessary to install one. Therefore, two types of non-inverting amplifiers and non-inverting amplifiers do not need to be provided, and in the case of the configuration in which the A / D conversion of the video signal is performed digitally, such a polarity switching circuit can be realized with a small component point. .

Video data that has passed through the digital polarity switching circuit needs to be D / A converted into R, G, and B video signals. Therefore, by operating the latch circuit provided at the front end of the D / A converter in accordance with the color order in the read data string, the D / A converter corresponding to various data is supplied and converted into an analog video signal by each D / A converter. . The analog video signal thus obtained is a video signal for a high-speed sequential system, and a video signal corresponding to one gate line can be supplied to the source driver in 1/2 horizontal period time.

In the above-described configuration, analog video signals of three colors, R, G, and B, are converted into video digital data using A / D converters installed corresponding to respective colors, and a three-state buffer provided after each A / D converter. After adjusting the operation timing of, convert the RGB three-color video signal into one data string, perform the desired digital processing, and then adjust the operation timing by using the latch circuit of one data string again. A configuration for dividing a variety of digital video data into an analog video signal for the installed D / A converter is taken.

With the above configuration, the digital processing circuit portion between the three-state buffer and the latch circuit can perform batch processing without dividing the various data, and can reduce the part score. Next, an embodiment of this invention will be described in detail with reference to the drawings.

Now, as another embodiment of the present invention, as shown in FIG. 11, 640 pixels in the horizontal direction of the liquid crystal panel 147, 640 pixels in the vertical direction, and (480) pixels in the vertical direction are used. Consider the case where the filter array is a delta array as shown in FIG. Further, as a source driver for driving the liquid crystal panel 147, as an example, four lines for driving each of four groups in which the source lines of the liquid crystal panel are the radix line, the even line, and the first half and the second half of the source line are driven. Consider a configuration in which the source drivers 143, 144, 145 and 146 are installed.

That is, referring to FIG. 11, the source driver 143 applies a signal to the odd source line of the first half of the source line, and the source driver 144 supplies the video signal to the odd line of the second half of the source line. . The source driver 145 supplies the video signal to the source line of the first half, and the source driver 146 supplies the video signal to the even source line of the second half. Here, 640 source lines are provided as described above, and it is assumed that numbers 1 to 640 are sequentially assigned to each source line as in FIG. 4. In addition, in the structure of FIG. 11, R, G, and B of the liquid crystal panel 147 represent the color of a pixel, respectively, and the number attached below each B, G, and R has shown the number of a source line. The scan driver for driving the gate line is not shown.

As described above, the number of source lines of the liquid crystal panel 147 is 640, similar to the number of horizontal pixels, and the number of gate lines is 480, which is the same as the number of vertical pixels. In the source line, since the color filters are delta-arranged, the liquid crystal panel 147 is arranged in a zigzag shape as shown in FIG. 17, and one source line drives a liquid crystal of the same color in each gate line. Is taken.

11, the contact between the signal output terminals of the source drivers 143 to 146 and the source lines in the liquid crystal panel 147 are arranged so as not to cross each other.

As specifically shown in FIG. 12, the arrangement of the pixels 48 of the liquid crystal panel 47 is shifted 1.5 pixels between the odd gate line and the even gate line.

Each of the source drivers 143 to 146 for driving each source line of the liquid crystal panel 47 has a configuration as shown in FIG.

Referring to FIG. 13, the source driver outputs the video signal in response to the shift register 149 and the shift enable signal at the shift register 149, which are shifted one by one at the output terminal of the start pulse ø ₃ . Samples and holds the video signal imparted via analog switches 150-1 through 150-m and analog switches 150 through 150-1 through 150-m that carry each of V1 through V3, and all An analog sample / hold circuit 51 is provided for supplying their retained video signal to the corresponding source line at the time of retaining the signal for the source line.

The analog switch 150 is sequentially turned on in response to the selection activation signal in the shift register 149 and transfers the corresponding video signal to the analog sample / hold circuit 151. Each of the video signals V1 to V3 corresponds to a video signal of each of the colors R, G, and B, and the video signals of the respective colors are transmitted in parallel. Therefore, in this configuration, for example, when the R video signal is transmitted to the analog sample / hold circuit 151, the video signals of the remaining colors are not transmitted, but only one color, that is, a video signal of one pixel. Passed through the log switch 150 to the analog sample / hold circuit 151.

The shift register 149 drives one-fourth of the liquid crystal panel, i.e., one-fourth of the number of 640 pixels of one gate line, and thus has a 160-stage (m = 160) shift register configuration. The analog sample / hold circuit 151 performs sampling and hold operations in parallel with the operation of supplying the signal transmitted through the analog switch 50 to the source line.

FIG. 14 shows a specific configuration of the line memory circuit 142 (see FIG. 11) for supplying a video signal to each of the source drivers 143 to 146. FIG. Referring to FIG. 14, the line memory circuit 42 includes two rows (two gate lines) for odd gate lines and even gate lines in the video signals V _B , V _R , and V _G in one horizontal period. The minute video signal is derived from a block 100 and a data thermal conversion circuit for deriving a data string in which the video signals of the two gate lines in the block 100 are selectively aligned with the video signals of the even source lines. 113), the video signal data for the mantissa source line and the video signal data for the even source line in the data column conversion circuit 113 are further divided into the video signal data for the first source line and the video signal data for the second source line. 8 groups of alternating video signal data for odd-numbered gate lines, even-numbered gate lines, odd-numbered source lines, even-number fractional lines, first-order source lines, and second-order source lines, respectively. Polarity switching circuits 127 and 128 for switching the signal polarity of the video signal data in the memory block 200 and the memory block 200 to the even gate line and the odd gate line, and the polarity switching circuit 127. And a block 300 for receiving video signal data at 128 and deriving the video signal data of three columns of each of R, G, and B in the video signal data column of the column.

A block 100 for deriving the video signal data for the two gate lines is an A / D converter 101 for sampling each of the analog video signals V _G , V _R , V _B at a predetermined timing and converting them into digital signals. ) And 106, and the three-state buffers 107 to 112 which input and output each of the A / D converters 101 to 106 at a predetermined timing. The A / D converters 101 to 103 are for exposing video signal data corresponding to one gate line (for example, odd gate line), and the A / D converters 104 to 106 are for the other gate. To derive video signal data of a line (e.g., even gate line). The buffers 107 to 109 and the buffers 110 to 112 have different timings for inputting and outputting signals in each group, and three columns of video signal data (corresponding to R, G, and B signal data) are stored in one column. Convert to a column of data.

The memory block 200 performs a pair of write and read operations to a memory and a pair of memory units for storing a video signal to be supplied to a memory even source line for storing signal data to be supplied to an odd source line. In order to do this, the same memory includes a pair of four line memories 118, 119, 120, and 121 in total. The memories 118 and 119 operate in pairs, and the memories 20 and 21 operate in pairs. That is, while data is written to the memory 118, 119, data is read from the memory 20, 21. The memory 18, 20 stores, for example, video signal data to be supplied to the odd source line.

Between the data column converter circuit 113 and the memory 118, 120, the data column converter circuit 113 receives the three-state buffers 114, 115, buffers 114, and 115 that receive the output data stream. A data bus multiplexer 25 for selectively transferring one of the outputs to one of the memories 118 and 120 and connecting an output bus of a memory in which data is not written to the polarity switching circuit 27; Is installed. The outputs of the memory 119, 121 and the data string conversion circuit 113 are read from the three-state memories 20, 21 to be transferred. The memory 18, 20 stores, for example, video signal data to be supplied to the odd source line.

The three-state buffers 114, 115, buffers 114, and 115 between the data column converter circuit 113 and the memory 118, 120 receive the output data stream from the data column converter circuit 113. A data bus multiplexer 25 which selectively transfers one of the outputs to one of the memories 118 and 120 and connects the output bus of the memory in which data is not written to the polarity switching circuit 27; Is installed. Between the memory 119, 121 and the data heat conversion circuit 113, the output of the data heat conversion circuit 113 is transferred to the three-state buffers 116, 117, and the memory 119, 121. A data bus multiplexer 26 is provided which selectively connects the data write paths in the buffers 116 and 117 and the read paths in the memory 119 and 121 to the polarity switching circuit 28. The output of the three state buffer 114 is delivered to the memory 118, and the output of the three state buffer 115 is delivered to the memory 120. The output of the 3 state buffer 116 is transferred to the memory 119, and the output of the 3 state buffer 117 is transferred to the memory 121. The data bus multiplexer 125 transfers the output of the memory 120 to the polarity switch 127 while data in the buffer 114 is being written to the memory 118. Similarly, data bus multiplexer 126 transfers the output of memory 121 to polarity switching circuit 128 while, for example, the output of buffer 116 is being written to polarity switching 119. This configuration prevents contention between the write data and the read data on the data bus.

Each of the memories 118 to 121 is a write address generating circuit 123 for giving a write address, a read address generating circuit 124 for giving a read address of the memories 118 to 121, and a write address. Selectively transmits address signals from the generation circuit 123 and the read address generation circuit 124 to the memory 118, 119, and the memory 120, 121 according to the read operation and the write operation of each memory, respectively. An address bus switching circuit 122 is provided.

The address bus switching circuit 122 transmits the output of the address generating circuit 123 to the memories 118 and 119 when the memories 118 and 119 perform a write operation, and simultaneously generates a read address. The address in the circuit 124 is transferred to the memory 120, 121. That is, the address bus switching circuit 22 transfers the read address in the memory read address generation circuit 124 performing the read operation, and transfers the write address in the write address generation circuit 123 to the memory performing the write operation. To pass.

The block 300 is a latch circuit, for example, a D-type flip-flop, for converting one column of data output through the polarity switching circuits 127 and 128 into three columns of video signals (R, B video signals). 129 to 134 and D / A converters 135 to 140 for converting each of the outputs of the latch circuits 129 to 134 into analog signals at predetermined timings. The latch circuits 129 to 131 and the latches 132 to 134 have different latch timings in respective groups, and the video signals of the corresponding colors in the polarity switching circuits 127 and 128 respectively. Only data is latched. That is, the latch circuits 129, 132 latch the B video signal data, the latch circuits 130, 133 latch the R video signal data, and the latch circuits 131, 134 the G video. Latch the signal data.

에 응답해서 동작 타이밍이 규정되며, 미리 정해진 타이밍으로 각종 제어 신호를 도출하는 제어 회로(141)가 설치된다. 다음에 각 회로의 블록의 동작에 대해서 설명한다. 단, 이하의 설명에 있어서는 설명을 간단히 하기 위해서 전술의 실시예의 설명과 마찬가지로 한쪽의 회로의 동작 및 우수의 게이트 라인 또는 기수의 게이트 라인 및 1짝의 메모리의 동작에 대해서만 설명한다.Clock signal for line memory to control operation timing of each block

In response to this, the operation timing is defined, and a control circuit 141 for deriving various control signals at a predetermined timing is provided. Next, the operation of the block of each circuit will be described. However, in the following description, for the sake of simplicity, only the operation of one circuit and the operation of an even gate line or an odd gate line and a pair of memories will be described in the same manner as in the above-described embodiment.

First, with reference to FIGS. 15 and 16, an operation of deriving digital video data for even gate lines and odd gate lines from a video signal in one horizontal period will be described. Referring to FIG. 15, a configuration for deriving video newlywed data corresponding to one gate line is shown.

에 응답해서 데이터의 취입 및 출력 동작을 행하며, 버퍼(157)는 제어 신호

에 응답해서 데이터의 취입 및 출력 동작을 행한다.Referring to FIG. 15, the A / D converters 152 to 154 that perform A / D conversion operations in response to the line memory clock ø ₂ , and a three-state buffer that take in and output data at different timings, respectively. 155 to 157 are shown. The three-state buffer 155 takes in and outputs data in response to the control signal gate GB, and the buffer 156 controls the control signal.

In response to the taking and outputting of the data, the buffer 157 receives a control signal.

In response, data is taken in and outputted.

,

,

가 ＂L＂레벨로 되었을 때 부여되는 신호를 출력한다. 이 제어 신호

,

,

제16e,f,g에 도시되듯이 클록 신호 ø₂를 동기하며 또한, 서로 겹치지 않는 3의 클록을 구성하고 있으며, 따라서 버퍼(155) 내지 (157)에서 출력되는 데이터 열을 액정 패널의 칼러 필터의 색배열과 같은 순서를 갖는다.The analog video signal is sampled at the granularity of the line memory clock ø ₂ in each of the A / D converters 152 to 154 at each of V _B , V _R , and V _G , and at the next arrival of the clock ø ₂ . In response, it is output as digital video data. Each of the three-state buffers 155 to 157 is a control signal, respectively.

,

,

Outputs the signal given when the signal reaches the L level. 2 control signal

,

,

As shown in the 16th, f, and g, the clock signal? ₂ is synchronized with each other, and a clock of 3 does not overlap with each other. Thus, the data streams output from the buffers 155 to 157 are color filters of the liquid crystal panel. It has the same order as the color array of.

The A / D converters 152 to 154 provided in correspondence with R, G, and B are driven by the same clock. However, in the odd line and even line of the gate line, the clock phase is 180 degrees different for the following reasons. In the above-described configuration, video signal data for one pixel in the horizontal direction of the liquid crystal panel is sampled and output to one clock of the A / D converter. On the other hand, in the case of the color filter of the delta arrangement, the arrangement of the color pixels is shifted by 1.5 pixels in the odd lines and even lines of the gate lines. This shift of 1.5 pixels is a shift of 1.5 clock cycles at clock signal? ₂ . The difference of 1.5 clock periods is equal to the clock phase 189 ° added to the shift of one clock period, and the shift of the clock period is equal to 360 °, that is, 0 °. Therefore, the clock phase of the A / D converter may be shifted 180 degrees for the odd lines and even lines of the gate lines. Accordingly, the buffers 155 to 157, that is, the buffers 107 to 109 of FIG. 14 and the buffers 155 to 157 are shifted from each other by half a clock of the line memory clock ø ₂ . ) to (since 157) the line memory clock outputs the first video signal data on the color of the first clock ø ₂ is in, as illustrated in Figure 16k is a row of composite data string is assigned to the data converting circuit 113. By using one digital data string in this manner, it is possible to perform high-speed digital processing in three colors collectively and to reduce the circuit score.

The digital video data streams for the odd gate lines and even gate lines formed from the buffers 107 to 109 and the buffers 110 to 112 are provided to the data column conversion circuit 113, where Digital signal data strings applied to the odd lines and digital signal data strings applied to the even lines of the source lines. Next, the specific configuration and operation of the data column converter circuit 113 will be described with reference to FIGS. 17 and 18. FIG.

The latch circuit 159, which receives the video signal data string derived for the odd gate line and receives the video signal data string derived for the line, for example, becomes a D-type flip-flop. And a digital bus switching circuit 160 for receiving signals from the latch circuits 158 and 159 and switching the transmission path in response to the selection circuit SEL, and for latching signals from the digital bus switching circuit 160. A latch circuit 61 that is a D flip-flop is provided.

The latch circuit 161 outputs a data string to be applied to the odd source line, and the digital bus switching circuit 160 outputs a digital data string to be applied to the even source line through the other data bus. The latch circuits 158, 159, and 161 perform a latch operation in response to the line memory clock phi ₂ . The selection signal SEL applied to the digit bus switching circuit 160 has a period twice as long as the line memory clock ø ₂ . Next, the operation will be described.

As shown in Fig. 18, the output of the digital signal data for the odd line of the gate line and the digital signal data string for the even line of the gate line of the digital signal data for the even line of the gate line are shifted by 1.5 clocks (18b and 18b). See also c). The digital signal data columns for odd-numbered gate lines and the digital signal data columns for even gate lines shifted 1.5 clock phases out of each other are caused by the latch circuits 158 and 159, respectively, and the same is latched by the line memory clock ø ₂ . . Since the latch circuits 158 and 159 are constituted by D flip-flops, the data strings output from the latch circuits 158 and 159 are shifted by one clock (see also 18d and e). The data bus shifted by one clock phase is replaced by the digital bus switching circuit 160 in response to the selection signal SEL. That is, the digital data string and the even source line to be applied to the odd source line as shown in FIG. 18g, h of the digital bus switch circuit 160 by switching the connection path of the input / output in the digital bus switch circuit 160 are shown. The digital data stream to be applied is output.

At this time, the digital data for the even gate line and the odd gate line are shown alternately in each data column. Since the output signal from the digit bus switching circuit 160 is shifted by one clock phase as shown in FIG. 18, when writing the digit data as it is to the memory, it is necessary to perform each write operation by one clock. The read address of the memory must also be generated by one clock bit. Therefore, when this structure is taken, a disadvantage arises in that the circuit scale becomes large.

Therefore, in order to write data to the memory without correcting these clock shifts, a latch circuit in which the digital signal data strings of which the phase of one clock phase in the output signal data strings in the digital bus switching circuit 160 is advanced is a D-type flip-flop. By latching again at (! 61) and delaying the first half of the clock, it is possible to match the timing of the video signal data string to be applied to the even source line and the video signal data string to be applied to the odd source line. As a result, when writing digital data into the memory, each write operation (for odd source lines and even source lines) can be performed simultaneously, and a write address for the memory is generated by one write address generating circuit, respectively. Can be distributed to the memory of the component, thereby reducing the number of parts. Next, the write and read operations of the data in the memory block 200 will be described.

Since the video signal needs to be processed continuously, two odd-numbered source line memories and two even source line memories are provided, and the read and write operations of each memory are switched every horizontal period. The respective capacities of the memories 118 to 121 can be obtained from the write address, read address, first half of source line, second half bit X, odd line of gate line, and even line change bit y. If the number N of pixels in one horizontal period is 640 as described above, if four source drivers are installed, the first and second transition bits X of the source line are X≥log ₂ (N / 4) = log ₂ ( 160), X = 8.

On the other hand, the odd line and even line switching bit y of the gate line have the capacity to store the data of all the source lines as the address area for each gate line since the next gate line is scanned when the data of all the source lines 640 are processed. Y = X + 1 = 8 + 1 = 9 since it is necessary.

Therefore, the storage capacity of each memory ranges from 2 (y + 1) to (1024) words. This word length is determined according to the resolution of the A / D converter and the D / A converter.

The write operation and read operation to the memories 118 to 121 are switched every one horizontal period. The three-state buffers 114 to 117 and the memo pads 118 to 121 provided at the front end of each memory so as to selectively switch data writing and reading operations to the memories 118 to 121 and to avoid collisions between the read data and the write data. The data bus multiplexers 125 and 126 installed in respective read paths of are selectively controlled to write and read data.

That is, in the case of the data write operation to the memories 118 and 119, the three-state buffers 114 and 116 provided immediately before the memories 118 and 119 are enabled and data string conversion is performed. The video signal data strings in the circuit 113 are written into the memory 118, 119. Conversely, in the case of performing the data read operation of the memory 118, 119, the three state buffers 114, 116 provided at the front end are disabled and read from the memory 118, 119. The obtained data does not collide with the data in the data string conversion circuit 113.

In addition, the data bus multiplexers 125 and 126 provided at the rear end of each memory (the rear end of the read path) are always connected to the data bus to which the memory in which the read operation is performed among the memories 118 to 121 is connected. The selected data bus is connected to the polarity switching circuits 127 and 128 at the next stage. Therefore, the switching control signal ø ₂ provided to the data bus multiplexers 125 and 126 becomes a control signal in synchronization with the write read control signal RW provided to the memories 118 to 121, and 2 every one horizontal period. It is switched with the connection path of the data bus.

The write address designating the write position from the write address generation circuit 123 to the memory is the odd line of the gate line, even according to the output timing of the data output from the data string conversion circuit 113 as shown in FIG. 19A. The line switch bit y is reset and incremented by one while repeating the set. Similarly, the first half of the source line and the second half transition bit x are reset in the first half horizontal period and are set in the second half horizontal period. When the switch bit x is switched, the &quot; lower address (address excluding the switch bits x and y) is reset.

Specifically, the recording address of the first half horizontal period is 0,2 ^y +0,1,2 ^y +1,... N / 4-1,2 ^y + N / 4-1, and the second half of the horizontal period is 2 ^x +0,2 ^x +2 ^y +0,2 ^x +2 ^y +1,... 2 ^x + N / 4-1,2 ^x +2 ^y + N / 4-1. As described above, when the number N of pixels in one horizontal period is 640, as shown in FIG. 19A, the write addresses generated in the first half horizontal period are 0.512, 1,513,... The second half of the horizontal period is (256), (768), (257), (769),... 415, 927. As shown in Fig. 19A, video signal data for odd source lines and video signal data for even gate lines are shown as a table, and the write addresses are switched to the switching bits x and y, respectively. Therefore, as shown in FIG. 19B, in the first half horizontal period, video signal data is alternately recorded in the area A ₁ and the area B _{1 of the} memory, and in the second half horizontal period. In this case, video signal data is recorded alternately into the area A ₂ and the area B ₂ of the memory. Here, in Fig. 19B, the area A is an area for receiving the video digital signal area for the even gate line. Therefore, in each of the memory for odd source lines and the memory for a plurality of source lines, the area is divided into four, divided into eight areas, and video signal data is stored.

The address for reading the digital data in the memories 118 to 121 is generated in the read address generating circuit 124 and transferred to the memory during the read operation via the address bus switching circuit 122. The read addresses generated by this read address generating circuit 124 are incremented one by one while resetting and setting the first and second switching bits x in the entire source line as shown in FIG. 20A. If the odd line of the gate line of the first half horizontal period is the odd number of the gate line and the even line switching bit y, the odd number of the gate line is reset if the second half horizontal period is the even line of the gate line. The line, even line switch bit y is set. That is, at the time of data reading, the switching bit y is reset if the gate line is an odd line, and the switching bit y is set if the gate line is an even line.

Here, if the order of colors arranged in the color filter of the liquid crystal panel is B, G, and R, they are stored in the memory in this order. Therefore, the color order of the video signal data read out by the above-described read address is as follows: B (0), R (256), R (1), G (257), B (258). The color order of the data read on the even source line side is G (0), B (1), R (257), R (2), and G (258). Note that the number in parentheses indicates the address. Therefore, when this read video digital signal data string is D / A-converted as an analog video signal, the same color signal is adjacent to each other, so that a margin for selectively transferring the signal to a source driver for driving the liquid crystal panel is provided. Will not exist.

Therefore, during data reading, the first and second transition bits x of the source line are incremented one by one while repeating the set and reset in reverse to the data write. In other words, if the data of the latter half of the source line is inputted to the source driver, the radix line side of the source line has B, G, R, B, G arrangement of video digital data, while the even line side of the source line has B, G, R, G, and R. This arrangement becomes the same as the arrangement order of the colors of the color filters of the liquid crystal panel, and the signal distribution to the source driver can be easily performed.

Specifically, if the first half horizontal period is video signal data for the odd gate line, the read address is 2 ^X +0,0,2 ^X +1,1,... When 2 ^X + N / 4-1, N / 4-1, the read address is 2 ^y +2 ^x +0.2 ^y +0.2 for digital video data in which the second half horizontal period is for the even line of the gate line. ^y 2 ^x +1.2 ^y +1,... 2 ^y +2 ^x + N / 4-1,2 ^y + N / 4-1.

In fact, when the above values are specifically shown, as shown in FIG. 20A, the first half horizontal period has read addresses 256, 0, 257, 1,... (415), (159), and the read addresses of the second half horizontal period are (768), (512), (769), (513),... , 927 and 671. That is, as shown in FIG. 20B, in the case of the odd source line, data is sequentially read out in order of the regions A ₂ and A ₁ , and in the case of the odd gate line, the regions B ₂ and B _4. The data is read out alternately in the order of). The same applies to the memory for the even source line, and in the same manner as in FIG. 20B, the data is sequentially alternated in the order of each region A ₂ ′ (A ₁ ′) or (B ₂ ′), (B ₁ ′). Is read.

The address is generated as described above, and the read address and the write address for the memory can be the same address for any of the memory for the odd line of the source line and the memory for the even line of the source line. Each of the address generating circuits is provided, and the recording and reading of the video signal data can be performed by simply distributing the addresses in the address generating circuits via the address bus switching circuit 122. The data read through the data bus multiplexers 125 and 126 is inverted in each bit value of the digital video signal data by the digital polarity circuits 127 and 128. FIG. 21 shows a specific example of the digital polarity switching circuits 127 and 128. As shown in FIG.

Referring to FIG. 21, the digital polarity switching circuit has eight E _x -OR gates 162-(1) to (162)-(8). The configuration shown in FIG. 21 shows a case where the video digital signal data has an 8-bit configuration, that is, when the digital data of one pixel is 8 bits wide. The polarity switching signal PC is applied from the control circuit 141 to one input of each of the E _x -OR gates / 62-1 to 162-8. The E _x -OR gate normally outputs a signal of the "high (high)" level when the bit values of its inputs are inconsistent, and the "low" level when the bit values of both inputs match. Outputs the signal of. Therefore, when the polarity switching signal PC is? L, each of the E _x -OR gates / 62-1 to (162) -8 passes the input video digital signal data as it is, and when the polarity switching signal PC is? H ＂. Inverts the bit value and outputs the given video digital data. As shown in Fig. 22, the polarity switching signal PC switches its signal level in the first half horizontal period and the second half horizontal period. That is, the period of the polarity switching signal PC is one horizontal period. Therefore, the polarity of the signal is shifted by 180 degrees in the first half horizontal period and the second half horizontal period. As a result, the polarity of the signal can be reversed in the even gate line of the odd gate line, and signal switching in the high speed line sequential method can be obtained. The signal passing through the polarity switching circuits 127 and 128 is one column of digital video data columns. Since this digital data column of one column is distributed to each of the D / A converters 135 to 140 provided for each of R, G, and B colors, the latch circuit 129 in which the digital signal becomes a D-type flip-flop in the data column. To 134), which are then latched at different timings and converted into three rows of digital video signal data in parallel of the color correspondences of R, G, and B, respectively. The path for deriving the video signal to be transmitted to the odd source line and the path for deriving the video signal to be transmitted to the even source line have the same operation, and thus only one operation will be described with reference to FIGS. 23 and 24. .

Referring to FIG. 23, a latch circuit 163 serving as a D flip flop for latching a B signal, a latch circuit 164 having a D flip flop for latching an R signal, and a latch circuit serving as a D flip flop for latching a G signal Think of (165). Each of the latch circuits 163 to 165 is provided with A / D converters 166 to 168 for converting each latch output to an analog signal. The latch circuit 163 performs a latch operation in response to the lay control signal LB, the latch circuit 164 performs a latch operation in response to the latch control signal LR, and the latch circuit 165 responds to the latch control signal LG. The latch operation is performed. These control signals LB, LR, and LG form three-phase clock signals that do not overlap each other by their phases being shifted, as shown in Figs. 24C, d, and e, respectively. The period of the signal has twice the period of the line memory clock. First, as shown in FIG. 24B, the synthesized data string output from the data polarity inversion circuit is R, B, G, R,... This is called the array order of.

의 3클록마다 래치 동작을 행하므로 각 래치 회로(163) 내지 (165)의 데이터 보유 기간은 라인 메모리 클록

의 3클록 기간이 된다. 각 D/A 변환기(135) 내지 (140)(166 내지 168)의 출력 신호는 각각 대응하는 소스 드라이버(143) 내지 (146)로 전달된다. 제11도에 도시하는 소스 드라이버 (143) 내지 (146) 중, 전반의 소스 라인으로 접속되는 소스 드라이버(143),(145)는 동일 클록으로 동작하며, 후반의 소스 라인에 접속되는 소스 드라이버(144),(146)는 동일 클록으로 동작한다. 따라서, 기수 소스 라인에 관해서 후반의 소스 드라이버와 전반용의 소스 드라이버가 교대로 데이터의 들임을 행하고, 마찬가지로 우수의 소스 라인에 접속되는 소스 드라이버(145),(146)에 있어서도 교대로 데이터의 수신을 행한다.In this case, the latch circuit 164 performs the latch operation in response to the control signal LR, and the latch circuits 165 and 163 perform the latch operation of the data in this order. Each of the latch circuits 163 to 165 each has a line memory clock.

Since the latch operation is performed every three clocks, the data retention period of each latch circuit 163 to 165 is a line memory clock.

3 clock periods. The output signal of each D / A converter 135-140 (166-168) is passed to the corresponding source driver 143-146, respectively. Of the source drivers 143 to 146 shown in FIG. 11, the source drivers 143 and 145 connected to the first source line operate at the same clock, and the source drivers connected to the second source line ( 144 and 146 operate on the same clock. Accordingly, the source driver for the latter half and the source driver for the first half alternately input data with respect to the odd source line, and similarly receive data at the source drivers 145 and 146 connected to the excellent source line as well. Is done.

에 응답해서 각 D/A 변환기9135내지 140)에서 출력된 데이터가 대응의 소스 드라이버내의 아나로그 샘플/홀드 회로(151)로 샘플 홀드된다.Clock signals for driving each of these source drivers 143 to 146

In response, the data output from each D / A converters 9535 to 140 are sampled and held in the analog sample / hold circuit 151 in the corresponding source driver.

의 주기는 라인 메모리용 클록

의 주기의 2배를 가지고 있으며, 각 소스 드라이버는 배속선 순차 방식 및 인터레이스 방식과 마찬가지의 동작 속도로 동작하는 것이 가능해진다.At this time, as shown in FIG. 24 (j) and (k), the clock of the source driver

Period is clock for line memory

It has twice the period of, and each source driver can operate at the same operation speed as the double speed sequential method and the interlace method.

That is, in the source driver connected to the odd source lines with reference to FIGS. 13 and 24, first, when the source driver for driving the second source line is operated, the R signal R321 is sampled, and then the source of the first half. The source driver for line driving operates and samples the B signal B1. Hereafter, G323, R3, B325, and G5 are sampled one by one. This sample operation is performed by sequentially turning on each of the analog switches 150 and 150-1 to 150-m included in each source driver. Therefore, even if the outputs of the respective D / A converters 166 to 168 and 135 to 140 are output at the same time, these signal lines are arranged in three rows in parallel, and are connected to the analog switches in turn, so that one of the three outputs is provided. Only the video signal corresponding to the color is sampled to the analog sample / hold circuit / 51. The analog sample / hold circuit 151 transfers the data onto the corresponding source line after all the sample / hold operations of the given signals with respect to the gate lines of one row are completed. The above operation makes it possible to drive the liquid crystal pulse in the high speed line sequential method while operating each source driver at the same operation speed as the conventional double speed line sequential method and the interbase method.

In addition, the division mode of the area of a display panel and the number of source drivers are not limited to the said embodiment.

As described above, according to the present invention, since the liquid crystal panel can be driven by one line memory circuit for three colors, it is possible to have an inexpensive low power consumption liquid crystal drive device with a simple configuration.

In addition, at least one pair of memories is used to record video data into one memory and to simultaneously read data from the other memory. The read video data is also used as a first driver and a second driver for driving the liquid crystal panel. By alternately transmitting to a driver, even when operating with a low speed clock, it is possible to have a liquid crystal driving device having excellent linearity that drives the liquid crystal panel at high speed equivalently.

Furthermore, the memory area is divided into regions of the even gate line, the odd gate line, the odd source line, the even source line, the first half source line and the second half source line to store color video data converted for each data in each area. If the predetermined order is read in order, the liquid crystal panel can be driven in a high speed line sequential manner while operating the liquid crystal panel driving source driver at the same operation speed and operation as the conventional double speed line sequential method and interface method, thereby improving horizontal resolution and assimilation. It is possible to obtain improved responsiveness and improved flicker, and it is possible to drive a large-screen high-definition liquid crystal panel with high quality with little component reception.

Claims (21)

An apparatus for driving a color liquid crystal display panel, wherein the display panel includes a plurality of color pixels in which predetermined colors are arranged in order in a matrix form formed in rows and columns, and pixels of the same color of the plurality of color pixels, respectively. The plurality of source lines are divided into at least first and second groups having a plurality of source lines connected to one column of the first column, and the first and second groups are again divided into first and second sub groups, respectively. In a color liquid crystal display panel passive device divided by: a means for transmitting a signal to each of said plurality of source lines, said signal transmitting means being added to each of said first and second groups of said source line, respectively First source driver means (33,35) and second source driver means (34,36) to be installed, wherein each of the first and second source driver means is connected to the first sub And first drivers 33 and 34 installed corresponding to the group and second drivers 35 and 36 installed corresponding to the second subgroup, wherein the first driver and the second driver alternately. A first signal supply means 37 and a second signal supply means for latching a given color signal numerically and corresponding to each of said first and second TTM driver means and for imparting a color signal to a corresponding source driver means; (38), wherein each of the first and second signal supply means receives a plurality of types of analog color signals provided in parallel and corresponds to a color order defined by a source line of a corresponding group. First contact means (39b, 39r, 39g, 40r, 40g, 41, 42) for converting to a digital data stream of the data; means (43, 44, 49, 50) for storing the output of the exchange means in order of address; The storage means is transmitted to the first subgroup A first area for storing data, and a second area for storing data transmitted to said second subgroup, said means (49, 51) for sequentially reading the stored data from said storage means; An alternating reading means for alternately reading data in said first area and said second area, said analog converting means for converting a read data string in said reading means into an analog signal and transferring it to a corresponding source driver means; (46 (b), 46r, 47b, 47r, 47g, l ₁ b, l ₁ r, l ₁ g), wherein the analog conversion means converts the read data stream into a parallel analog signal for each color. And a second converting means 46 (b), 46r, 46 (g), 47b, 47r, 47g, l ₁ b, l ₁ r, l ₁ g for converting and outputting the converted color liquid crystal display panel. drive. The first sub-group according to claim 1, wherein each of the plurality of source lines includes a source line having an odd number constituting the first group and a source line having an even number constituting the second group. A source line of a first half portion constituting the first portion and a source line of a second half portion constituting the second subgroup, wherein the alternate reading means includes the second region and the first region of the storage means in order. And a means (51, 49) for alternately reading out raw data. 2. The apparatus according to claim 1, wherein said storage means comprises at least first and second memories each having a capacity sufficient to store data to be transferred to one row of pixels, and said apparatus is again provided with said first and second memories. And means (45,52) for controlling the operation of said storage means to read data from the memory in parallel when data is written to one side of the memory. 2. A plurality of A / D conversion means according to claim 1, wherein said first conversion means is provided corresponding to each of a plurality of types of analog color signals provided in parallel, and converts corresponding analog color signals into digital signals. 39b, 39r, 39g, a plurality of buffer means 40b which are provided corresponding to each of the plurality of A / D conversion means and which output the corresponding A / D conversion means output at a predetermined timing and are also output. 40r, 40g), the plurality of buffer means are sequentially activated periodically and sequentially in the order of the color of the source line of the corresponding group, and receives the output of the plurality of buffer means, converts them into digital data strings, and converts them into the storage means. And a means (41,42) for giving said data string. 2. The plurality of latch means (46), 46r, 46 (g) according to claim 1, wherein the second converting means are provided in parallel with each other and latch the digital data read by the reading means at different timings. The plurality of latch means are for outputting a plurality of kinds of color signals in parallel, and the corresponding source driver means are sequentially and cyclically activated according to the order in which the color signals are embedded, thereby latching the given data. And D / A conversion means 47b, 47r, 47g for outputting and corresponding to each of the latch means and converting the corresponding latch means output into an analog signal, and to each of the D / A conversion means. And a means (1 lb, 1lr, 1 lg) correspondingly installed and for transmitting the corresponding D / A conversion means output in parallel to the associated source driver means. An apparatus for driving a color liquid crystal display panel, comprising: a plurality of column liquid crystal pixels arranged in a predetermined color order for the liquid crystal panel, and signal potentials of the plurality of liquid crystal pixels for transmitting signal potential to the plurality of liquid crystal pixels. It has a plurality of source lines for transmitting and a plurality of gate lines for transmitting a signal for activating one row of the plurality of liquid crystal pixels by intersecting the plurality of source lines in the direction, the same for one source line Color liquid crystal pixels are connected, and the plurality of source lines are continuously increased to be divided into a source line group of odd number, a source line group of even number, a first source line group, and a second source line group. A color liquid crystal display panel drive device with a number as follows, wherein said radix source line group and said even source First and second source driver means 143, 144, 145 and 146, which are installed in correspondence with each of the groups, each of the first and second source driver means being alternately activated, for transmitting signals to the first and second source lines. One source driver 143, 145 and second source drivers 144, 146 for transmitting signals to the latter source line, each of the first and second source driver means being of a color of the corresponding source line group. Means (149,150,151) for hatching a predetermined signal in the order of the arrangement order, and for delivering the latch signal to a corresponding group of source lines at a predetermined timing, and corresponding to one row of the plurality of pixels. Receiving a log video signal, deriving a data string so as to be displayed as pixels connected to the first row and the second row facing the first row from the received one row of video signals. Means (101,102, 103, 104,105,106,107,108,109,110,111,112,113), the video signal includes three independent color signals transmitted in parallel, and receives the signal data thermal derivation means output and receives the received video signal data in the first row and the second row. Means for dividing and storing the signal data transmitted to each of the odd source line group, the even source line group, the first source line group, and the second source line group (114, 115, 116, 117, 118, 119, 120, 121, 123, 141), and Means for first reading out data to be transferred to the pixels of the first row in series from among the stored data of the storage means, and then reading data serially to the pixels of the second row in the predetermined order (124, 141) and the reading means output data stream at a predetermined timing, so that the parallel is not the three colors. Means (129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140) for transferring to said first and said second source driver means when converted to said color signal, said transfer means latching and converting data transferred to said even source line of the read data stream And one latch converting means and a second latch converting means for latching and converting data transferred to said radix source line. The display panel of claim 6, wherein the display panel comprises a color filter of a delta array in which pixels of adjacent gate lines are arranged out of 1.5 pixels, and the digital data column derivation means receives three color signals in parallel, The first derivation means (101,102,103,107,108,109) for deriving the color signal to be transmitted to the pixel of one gate line in the form of a digital signal column, and the first derivation means are arranged in the order of the color order of the pixel connected to the first gate line. Means (107, 108, and 109) for deriving one column of digital data in which three color signals are arranged, wherein activation and complementation of the first derivation means are activated at a timing, and the three color signals in parallel are converted into the second color signal. Means for deriving one column of digital data columns in which the three color signals are arranged in the same order as the colors of the pixels connected to the gate lines of the plurality of means (104,105, 106,110,111,1) And a color liquid crystal display panel drive device. 8. The method of claim 7, wherein the digital data string derivation means receives first output of the first and second derivation means and deduces a first data column formed of digital data to be transmitted to the radix number source line. Means (158, 160, 161) and second data column conversion means (159, 160) for deriving a second data column formed of digital data to be transmitted to the radix number source line, wherein each of the first and second data columns is the first data column. And a data string in which data transferred to a pixel of a gate line and data transferred to a pixel of the second gate line are alternately arranged. 8. The apparatus of claim 7, wherein the first derivation means is provided corresponding to each of the three parallel analog color signals and converts the corresponding color signal into a digital signal in response to a clock signal. First to third buffers corresponding to each of the third A / D conversion means 101, 102, 103, 152, 153 and 154 and the first to third A / D conversion means, and selectively passing the output of the associated A / D conversion means. Means (107, 108, 109), wherein the first to third buffer means are in turn also activated cyclically, whereby the color sequence of the pixels in the first row is reduced. The third buffer means is also cyclically activated in turn, thereby leading to a series of digital data arranged in an order in accordance with the color order of the bulls in the first row, each of the three parallel analog color signals. Fourth, fifth, and sixth (a) / D conversion means (104, 105, 106) and the fourth through fifth signals, respectively, provided in correspondence with the signal of the corresponding color signal and converting the digital signal in response to the inverted signal of the clock signal. A fourth, fifth, and sixth buffer means (110,111,112) provided corresponding to each of the sixth (a) / D conversion means and selectively passing the corresponding A / D conversion means output; The sixth to sixth buffer means are sequentially and cyclically activated to derive the digital color signal data strings arranged in the order according to the color order of the pixels of the second gate line, and furthermore, the digital data from the first to third buffer means. And a data column having a timing difference of 1.5 pixels from the digital data strings from the fourth to sixth buffer means. 8. The digital data stream of claim 7, wherein the digital data stream from the first derivation means is advanced in a phase of 1.5 pixels from the digital data stream from the second derivation means. First latch means 158 for latching and outputting digital data from the derivation means in response to a clock signal, and second replacement means 159 for latching and outputting digital data from the second derivation means in response to the clock signal. And a data string formed of data to receive the output of the first and second derivation means and to replace the outputs of the first and second derivation means in response to a selection signal to be transmitted to the radix source line. Thermal conversion means (160) for deriving the data stream to be given to the even source line and digital data for the radix source line from the thermal conversion means; And a third latch means (161) for latching a column in response to said clock signal. The memory device according to claim 8, wherein the means for storing comprises: first memory means (118, 120) for storing the digital data for the odd source line, the first memory means having a first memory area and a second memory area. Second memory means (119,121) for storing digital data for source lines, said second memory means having a first half memory region and a second half memory region, said first data column converting means outputting said first half of said first memory means First recording means (122, 123, 144) for alternately writing to the memory area of the memory area and the latter memory area, and the output of the second data string conversion means alternately writing the second memory means and the first half and the second half. Second recording means 122, 123, and 124 for the purpose of providing data writing lines to the corresponding memory means. A color liquid crystal display panel drive apparatus, characterized by sharing means (123) for generating a predetermined address, and writing data from the write address generating means to corresponding memory means at the same time. 12. The apparatus according to claim 11, wherein each of said first and second memory regions of said first and second memory means is further divided into first and second sub memory regions, and said input address generating means. In the first half memory period during which one gate line is activated, data is alternately stored in the first sub memory area of the first memory area and the first sub memory area of the second memory area. An address is generated so as to be input, and in the second half period between the first horizontal syringes, data is alternately stored in the second sub memory area of the first half memory area and the second sub memory area of the second half memory area. Color liquid crystal display panel drive apparatus, characterized in that for generating an address to be input. 8. The data according to claim 7, wherein the reading means includes, in the storage means, data to be transferred to the source line of the first half of the source line group of the odd number of the first row, the latter half of the source line group of the odd number of the first row The data to be transferred to the source line of the first row, the data transferred to the source line of the second half of the source line group of the radix number of the first row alternately read, and after completion of reading the data for the first row, the second row First reading means (118, 120, 124, 141) for alternately reading the data transmitted to the source line in the first half of the source line group of the odd number and the data to be delivered to the source line in the second half of the source line group of the odd number of the second row; And from the storage means, data to be transferred to the first source line of the first excellent source line group in the first row to the second source line of the second excellent source line group in the first row. Reading data, and after completion of reading the data for the first row, the data to be transferred to the first source line of the first source line group in the second row and the source line group of the even row in the second row. And second reading means for alternately reading data to be transferred to the later source line of the data line, wherein the first and second readout data streams have the same color order as the color order of the pixels of the corresponding gate lines. Color liquid crystal display panel drive device having a. 13. The apparatus of claim 12, wherein the reading means comprises: first reading means (118, 120, 124, 141) for reading data from the first memory means, and the first means is the first memory means in the first half period of the one horizontal period. The data of the first sub-area and the data of the second sub-area of the first half of the memory area are alternately read, and further to the second half of the first memory means in the second half of the first horizontal period. Second reading means (119, 121, 124, 141) for sequentially reading the data of the second sub area, and sequentially reading data from the second memory means, and the second reading means is configured to perform the first horizontal scanning. Data alternately in the first sub memory area and the second sub memory area of the first half memory area of the second memory means in the first half period of the period; In the second half of the first horizontal period, data is alternately read from the first sub memory area and the second sub memory area of the second memory area of the second memory means. The first and second reading means share one read address generating means 124, and the first and second reading means read data at the same timing according to the same address from the read address generating means. A color liquid crystal display panel drive device. 7. The color liquid crystal display panel drive according to claim 6, further comprising means (127, 128) for receiving the data column from the reading means and inverting the polarity of the data each time the pixel data of one gate line share is received. Device. The apparatus of claim 15, wherein the inverting means comprises means for inverting each bit value of the received data. The method of claim 14, wherein the means for transmitting the source driver signal is output according to the color sequence of the driving source line of the first source driver means, which outputs the first reading means by latching the output at different timings. Sequentially and cyclically activated to latch a signal, provided correspondingly to each of said first to third latch means, and converting a corresponding latch means output into an analog signal and transferring it in parallel to said first source driver means. The first, second and third D / A conversion means 135, 136 and 137 and the fourth, fifth and sixth latch means 132, 133 and 134 installed in parallel with each other to latch and output the output of the second data reading means at different timings. ), The fourth to sixth latch means, cyclically activated to sequentially latch the given data according to the color patrol of the even source line, and the fourth to sixth latch means. Fourth, fifth and sixth (d) / A conversions corresponding to each of the sixth latching means and converting the corresponding latching means output into analog signals for transmission to the second source driver means in parallel. And a means (138, 139, 140). 7. The apparatus as set forth in claim 6, wherein said means for storing comprises: a pair of memory elements (118, 119) for storing data for said even source line group of data for said odd source line group, respectively, and said one pair Is provided with a data read operation when the memory device is performing a data write operation, and has another pair of memory devices 120 and 121 for 17 data write operations when the pair of memory devices are subjected to the data read operation. Color liquid crystal display panel drive device characterized in that. A method for driving a color liquid crystal display panel, wherein the display panel has a matrix shape formed in rows and columns, the plurality of color liquid crystal pixels arranged according to a predetermined color order, and a plurality of color liquid crystal pixels connected to each column. First and second source drivers each having a plurality of gate lines to which one color column of liquid crystal pixels are connected, and driving the first half and the second half of an odd-numbered source line around the pixel panel, respectively. And a third and fourth source drivers for driving first and second half portions of the even-numbered source lines, respectively, wherein the first analog color signals of three colors are received in parallel, and A first digital data string for an odd source line and a second digital data string for the even source line, wherein the first digital data string is And including three digital color signals arranged in accordance with the color order of the odd source lines, and wherein the second digital data sequence includes three digital color signals arranged in accordance with the color order of the even source line. And writing the first and second digital data streams to first and second memory devices in address order, respectively, wherein the first and second memory devices have first and second address areas. Alternately reading the first half region and the second half region from the first and second memory elements to derive a third digital data sequence and a fourth digital data sequence; Respectively converts the second and third analog color signals of three colors in parallel, and transmits the second analog color signals to the first and second source drivers. Transmitting a signal to the third and fourth source drivers, alternately activating the first source driver and the second source driver, and alternately activating the third and fourth source drivers, Accordingly, the second analog signal is held in the first and second source drivers, and the third analog color signal is held in the third and fourth source drivers, respectively. Panel driving method. A liquid crystal display panel comprising a plurality of color liquid crystal pixels arranged in accordance with an eighth array, a plurality of gate lines connected to one row of pixels, and a plurality of source lines transmitting signals to the plurality of pixels, respectively. And driving the display panel to activate two gate lines adjacent between the one horizontal syringes, the first source driver driving the first source line among the source lines of the odd number around the display panel and the odd number coder. A second source driver for driving the source line of the second half of the source line of the third source driver; a third source driver for driving the source line of the first half of the even numbered source lines; and a fourth source drive of the second source line of the source line of the even numbered numbers; In a method of driving a color liquid crystal display panel in which a source driver is provided and pixels of the same color are connected to one line, the three-color parallel connection is performed. In the first analog color signal, a first digital data string formed as a color signal transmitted to a pixel on a first gate line, and a color signal transmitted to a pixel on a second gate line facing the first gate line Derive a second digital data column, wherein the first digital data column and the second digital data column are out of phase by 1.5 pixels, and the first and second digital columns are pixels of one gate line. Comprising a digital color signal of three colors arranged in the same order as the color order of the step, correcting the phase difference of the first and second digital data strings by one pixel difference, the first digital data subjected to the phase correction A third digital data stream formed of three color signals transmitted from the column and the second digital data stream to the even number source line and the color to be transmitted to the radix number source line. Derive a fourth digital data string formed by the third and fourth digital data columns, wherein the third and fourth digital data columns include a data column in which data for the first gate line and data of the second gate line are alternately arranged; And wherein the third digital data column includes digital color signal columns arranged in an order in accordance with the color order of the even source line, and the fourth digital data column is in an order in accordance with the color order of the even source line. Providing an array of digital color signal columns arranged, matching phases of the third digital data stream and the fourth digital data stream, and converting the third digital data stream into a first memory element, and the fourth digital device. Respectively write a data string to a second memory element, wherein the first and second memory elements are arranged in a first memory area, a second memory area, and a third memory in an address order. A digital region having an area and a fourth memory area, wherein the writing step is alternately given to the first memory area and the third memory area of the first and second memory elements following the first half period between the first horizontal syringes; Inputting data, inputting data alternately provided to the second memory area and the fourth memory area in the second half period between the first horizontal syringes, and reading data from the first memory element; Deriving a fifth digital data string and simultaneously reading data from the second memory element to derive a sixth digital data string, wherein the reading step is performed in the first half period between the first horizontal syringes; Data is alternately read into the first memory area and the second memory area of the memory element, and further, the second half of the horizontal syringe is used. And reading data alternately into the third memory region and the fourth memory region, wherein the fifth digital data string is arranged in three colors arranged in an order in accordance with the color order of the radix source line. And a third digital color signal string arranged in an order according to the color order of the source line of the even number. Forming a second analog color signal in color parallel to the first and second source drivers, and forming a third analog color signal in three colors in parallel from the sixth digital data stream; And three latches arranged in parallel to transmit to the fourth source driver, wherein the second analog color signal forming step receives the fifth digital data stream simultaneously. And cyclically activating the means in turn, and also forming the third analog signal in turn also cyclically receiving three separate latch means arranged in parallel such that the sixth digital data stream is simultaneously received. And activating the first and second source drivers alternately to preserve the second analog signal in the first and second source drivers, and further, the third and fourth source drivers. Alternately activating to store the third analog color signal in the third and fourth source drivers. 21. The method of claim 20, further comprising converting polarities of the fifth and sixth digital data streams so that the polarities of the data are inverted relative to each other during the first half and the second half of the horizontal syringe. A liquid crystal display panel driving method, characterized in that.

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