KR920008893B1 - Image Data Path Control Circuit in Facsimile - Google Patents

Abstract

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Description

Image Data Path Control Circuit in Facsimile

1 is a conventional circuit diagram.

2 is a circuit diagram according to the present invention.

* Explanation of symbols for the main parts of the drawings

23: TPH 24: Vaginal / Parallel Converter

25 latch portion 26 8-minute cycle

27: modem 28: CPU

29: data transceiver 30: memory

31: parallel / serial converter 32: inverter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to facsimile, and more particularly to an image data path control circuit for controlling the printing and transmission / reception path of image data.

In general, the facsimile controls the printing and transmitting / receiving paths of the image data to be different.

The conventional printing and transmission / reception path control circuit is constructed as shown in FIG. Referring to FIG. 1, the conventional printing and transmission / reception path control operations are described below.

First, in FIG. 1, the CPU 8 processes image data by inter-processor communication with a system control processor (not shown) that controls the facsimile as a processor for processing image data. Also, for example, the CPU 8 may use Z8002 of ZILOG of the United States, and the Z8085 of ZILOG of United States of America may be used as the processor for controlling the system.

First, the case of operating in the copy mode. First, the Charge Coupled Device (CCD) 2 operates by a drive clock input from the drive clock generation circuit 1 to scan an original to generate an analog image signal corresponding to the amount of light reflected on the original. . At this time, the driving clock generation circuit 1 level shifts the clock generated by the clock generation circuit 13 to drive the CCD 2 and applies it to the CCD 2 as the driving clock signal. The avatar signal processing section 3 then digitally converts and binarizes the image signal input from the CCD 2 and outputs it as serial image data. The image data digitally converted and binarized by the talk signal processor 3 is applied to the serial / parallel converter 4. The serial / parallel converter 4 converts the serial image data into 8-bit parallel data in synchronization with the scan synchronous clock CKO input from the clock generation circuit 13 and applies it to the latch unit 6. The scan synchronous clock CKO is a clock for synchronizing image data according to scanning in the CCD 2.

At this time, the eighth frequency divider 5 divides the scan synchronization clock CKO into eighth to apply to the latch unit 6 and to the DMA controller 10 as a first DMA request signal DMARQ0. The latch unit 6 latches the parallel image data by the first DMA request signal DMRQ0. In addition, the DMA controller 10 requests the use of the data bus 101 by outputting the hold request signal HRQ to the CPU 8 in response to the first DMA request signal DMRQ0. The DMA controller 10 generates and applies the first DMA response signal DMAACKO to the latch unit 6 when the hold response signal HACK that allows the use of the data bus 101 is input from the CPU 8. The image data latched by the latch unit 6 is stored in the memory 11 via the data bus 101.

When the above-described operation is repeated and the storage of one line of image data is completed in the memory 11, the CPU 8 generates a print start signal and applies it to the eight divider 15. Then, the eighth frequency divider 15 divides the printing synchronization clock CK1 generated from the clock generation circuit 13 into eighth and applies it to the DMA controller 10 as the second DMA request signal DMARQ1. The printing synchronous clock CK1 is a TPH (Thermal Print Head) 14 which is a clock for synchronization of image data during printing. At this time, each time the second DMA request signal (DMARQ1) is input, the DMA controller 10 converts the image data stored in the memory 11 in units of bytes through the data bus 101 by one byte through the parallel / serial converter 7. The second DMA response signal DMAACK1 is generated and applied to the parallel / serial converter 7 at the same time. The parallel / serial converter 7 then converts the image data of one byte on the data bus 101 into serial data in synchronization with the printing synchronization clock CK1 in response to the second DMA response signal DMAACK1. Output to (14).

Therefore, the TPH 14 inputs serial image data from the parallel / serial converter 7 in synchronism with the printing synchronization clock CK1 through the buffer 16 under the control of the CPU 8, and displays an image according to the image data. Will print.

Second, the case of operating in the transmission mode will be described. First, the operation of generating image data for the original and storing the generated image data in the memory 11 in units of bytes is the same as in the copy mode described above.

When the image data of one line is completed in the memory 11 by the same operation as in the copy mode in the state where the relative facsimile and the protocol are established under the control of the system control processor, the CPU 8 After the image data stored in the memory 11 is taken in bar art units, the coding is performed and stored in the memory 11 again. The coded image data is inputted to the modem 12 to be modulated into an analog signal and then transmitted to the relative fax via communication lines L1 and L2.

Third, the case of operating in the reception mode will be described. The analog signal received from the relative facsimile via the communication lines L1 and L2 in the state in which the relative facsimile and the protocol are established under the control of the system control processor is demodulated by the modem 12 into digital image data. The modem 12 generates and applies a third DMA request signal DMARQ2 to the DMA controller 10 whenever one byte of data is received. The DMA controller 10 applies the demodulated image data through the data bus 101 by applying a third DMA response signal DMAACK2 to the modem 12 in response to the third DMA request signal DMARQ2. Store in Then, the CPU 8 takes demodulated image data stored in the memory 11, decodes the data, and stores the demodulated image data in the memory 11 again.

The above-described operation is repeated to print the image according to the image data stored in the memory 11 as the TPH 14 when one line of image data is stored in the memory 11. Same as in copy mode.

As described above, in the conventional printing and transmission / reception path control circuits, the performance of software is reduced by using the control by the DMA controller at the time of printing the read image and by using the DMA channel for the transmission and reception of image data. There was a problem. In addition, there is a problem in that the circuit configuration is complicated by using a DMA controller as well as a processor for controlling a system and a processor for processing image data.

Accordingly, an object of the present invention is to provide an image data path control circuit in a facsimile which can reduce the DMA channel when transmitting and receiving image data while controlling the DMA channel in the CPU and printing directly without using the DMA channel when printing image data. have.

Hereinafter, the present invention will be described in detail with reference to the drawings.

)에 의해 데이터버스(201)상에 출력하는 래치부(25)와, 상기 데이터버스(201)와 통신라인(L1,L2)에 접속되며 상기 데이터버스(201)상의 화상데이터를 아나로그신호로 변조하여 상기 통신라인(L1,L1)으로 전송하며, 상기 통신라인(L1,L2)을 통하여 아나로그신호가 입력될 때 이를 복조하는 동시에 제2DMA요구신호(DMARQ1)를 발생하며 복조데이터를 상기 송수신 DMA응답신호 (T/R

)에 의해 상기 데이터버스(201)상에 출력하는 모뎀(27)과, 상기 데이터버스(201)상의 화상데이터를 저장하기 위한 메모리(30)와, 시스템을 전반적으로 제어하며 복사모드시 상기 TPH(23)을 제어하여 프린팅을 하도록 하고, 송신모드시 상기 제1DMA요구신호(DMARQ0)에 응답하여 송수신 DMA응답신호(T/R

)를 인버터(32)를 통해 상기 래치부(25)에 인가하며 상기 메모리(30)에 저장된 화상데이터를 코딩하여 상기 모뎀(27)에 입력시키고, 수신모드시 상기 모뎀(27)의 상기 제2DMA요구신호(DMARQ1)에 응답하여 송수신 DMA응답신호(T/RDMAACK)를 상기 모뎀(27)에 인가하여 복조데이터를 상기 메모리(30)에 저장하고 디코딩한후 상기 TPH(23)를 제어하여 프린팅을 하도록 하는 CPU(28)와, 상기 데이터버스(201)와 상기 CPU(28) 사이에 접속되는 데이터 트랜시버(29)와, 상기 메모리(30)에 저장된 화상데이터를 상기 데이터버스(201)를 통해 입력하여 상기 프린팅동기클럭(CK1)에 동기하여 직렬의 데이터로 변환한후 상기 TPH(23)에 인가하는 병렬/직렬 변환기(31)로 구성한다.2 is a circuit diagram according to the present invention, which comprises a drive clock generation circuit 1, a CCD 2, and an image signal processing section 3, which scans an image of an original, converts it into a corresponding image signal, and then digitally converts and binarizes it. Image conversion means generated as serial image data, a clock used for conversion from the image conversion means to an image signal, and a scanning synchronous clock (CKO) for synchronizing the image data according to the scanning with the synchronization of the image data during printing. A clock generating circuit 13 which is a clock generating means for generating a printing synchronous clock CK1, and a TPH 23 for printing the generated image data in synchronization with the printing synchronous clock CK1 by a predetermined control; And a serial / parallel converter 24 for converting the generated image data into parallel image data in synchronism with the scanning synchronization clock CKO, and dividing the scanning synchronization clock by eight to output the first DMA request signal (DMARQ0). 8 frequency divider 26 and the parallel-converted image data latched by the first 1DMA request signal (DMARQ0), and latches the image data transmitted and received predetermined DMA response signal (T / R

Connected to the latch section 25 to be output on the data bus 201, the data bus 201 and the communication lines L1, L2, and the image data on the data bus 201 as analog signals. It modulates and transmits to the communication line (L1, L1), demodulates when an analog signal is input through the communication line (L1, L2), generates a second DMA request signal (DMARQ1), and transmits and receives demodulation data. DMA response signal (T / R

Modem 27 output on the data bus 201, a memory 30 for storing image data on the data bus 201, and the system in general and control the system. 23) to control printing, and transmit / receive DMA response signal (T / R) in response to the first DMA request signal (DMARQ0) in transmission mode.

) Is applied to the latch unit 25 through the inverter 32 and the image data stored in the memory 30 is coded and input to the modem 27, and the second DMA of the modem 27 in the reception mode. In response to the request signal (DMARQ1), a transmission / reception DMA response signal (T / RDMAACK) is applied to the modem 27 to store and decode demodulated data in the memory 30, and then control the TPH 23 to perform printing. CPU 28, a data transceiver 29 connected between the data bus 201 and the CPU 28, and image data stored in the memory 30 are inputted through the data bus 201. By converting into serial data in synchronization with the printing synchronous clock CK1, a parallel / serial converter 31 is applied to the TPH 23.

Hereinafter, an operation example of FIG. 2 according to the present invention will be described in detail.

First, in FIG. 2, the drive clock generation circuit 1, the CCD 2, the signal signal processing section 3, and the clock generation circuit 13 are the same as those of the conventional first drawing and the same reference numerals are used. In addition, unlike the related art, the present invention does not use a DMA controller and processes the image data at the same time as the CPU 28 controls the system without using a processor for system control and a processor for image data processing. The CPU 28 uses, for example, 80186 of INTEL Corporation of the United States.

First, the case of operating in the copy mode. First, the CCD 2 operates by a drive clock input from the drive clock generation circuit 1 to scan an original to generate an analog image signal corresponding to the amount of light reflected on the original. At this time, the drive clock generation circuit 1 level shifts the clock generated by the clock generation circuit 13 to drive the CCD 2 and applies it to the CCD 2 as a drive clock signal. The picture signal processing section 3 then digitally converts and binarizes the image signals input from the CCD 2 and outputs them as serial image data. The image data digitally converted and binarized by the talk signal processor 3 is simultaneously applied to the TPH 23 and the serial / parallel converter 24. At this time, the serial-to-parallel converter 24 is not copied because it is a copy mode.

The TPH 23 is controlled by a latch signal, a print start signal, and a motor drive signal inputted from the signal signal processing section 3 in synchronization with the printing synchronization clock CK1 and applied from the CPU 28. An image according to the image data is printed.

Therefore, the image data output from the signal signal processing section 3 is directly input to the TPH 23 to be a copy of the original.

Second, the operation in the transmission mode will be described. First, image data for the original is generated as in the copy mode. The serial / parallel converter 24 converts the serial image data into 8-bit parallel data in synchronization with the scan synchronous clock CKO input from the clock generation circuit 13, and applies it to the latch section 25. FIG.

)를 발생한다. 상기 송수신 DMA응답신호(T/R

)는 인버터 (32)에 의해 반전되어 래치부(25)에 인가됨으로써 래치부(25)에 래치된 화상데이터를 데이터버스(201)를 통하여 메모리(30)에 저장한다.At this time, the eight divider 26 divides the scan synchronous clock CKO into eight latches and applies them to the latch unit 25 and applies them to the CPU 28 as the first DMA request signal DMRQ0. The latch section 25 latches the parallel image data in response to the first DMA request signal DMRQ0. The CPU 28 also transmits and receives a DMA response signal (T / R) in response to the first DMA request signal (DMARQ0).

Will occur). The transmission / reception DMA response signal (T / R

) Is inverted by the inverter 32 and applied to the latch portion 25 to store the image data latched by the latch portion 25 in the memory 30 via the data bus 201.

When the above-described operation is repeated and the storage of one line of image data is completed in the memory 30, the CPU 28 takes the image data stored in the memory 30 in units of bytes and performs coding, and then the memory 30 Will be saved again. The coded image data is inputted to the modem 27 by being modulated into an analog signal while the relative fax and the protocol are established under the control of the CPU 28, and then transmitted to the relative fax through the communication lines L1 and L2. do.

)를 모뎀(27)에 인가함으로써 상기 복조된 화상데이터를 데이터버스(201)를 통하여 메모리(30)에 저장한다. 그러면 CPU(28)는 메모리(30)에 저장되어 있는 복조된 화상데이터를 가져와 디코딩을 한후 메모리(30)에 다시 저장하게 된다.Third, the operation in the reception mode will be described. The analog signal received from the relative facsimile via the communication lines L1 and L2 in the state in which the relative facsimile and the protocol are established under the control of the CPU 28 is demodulated by the modem 27 into digital image data. The modem 27 generates and applies the second DMA request signal DMRQ1 to the CPU 28 each time one byte of data is received. The CPU 28 transmits and receives a DMA response signal (T / R) in response to the second DMA request signal (DMARQ1).

Is applied to the modem 27 to store the demodulated image data in the memory 30 via the data bus 201. Then, the CPU 28 takes the demodulated image data stored in the memory 30, decodes the data, and stores the demodulated image data in the memory 30 again.

When the above-described operation is repeated to store one line of image data in the memory 30, the parallel / serial converter 31 prints the image data stored in the memory 30 by one byte. In synchronism with (CK1), the signal is serially converted and applied to the TPH 23. Accordingly, the TPH 23 inputs image data from the parallel / serial converter 31 in synchronism with the printing synchronization clock CK1 and is controlled by a latch signal, a print start signal, and a motor drive signal applied from the CPU 28. To print an image according to the image data.

As described above, the present invention has the advantage that the circuit configuration can be simplified while improving the performance of the software by reducing the DMA channel during transmission and reception while directly printing the read image data in the facsimile.

Claims (1)

Image conversion means for scanning an image of an original, converting it into a corresponding image signal, digital conversion and binarization to generate serial image data, a clock used for conversion from the image conversion means to an image signal, and image data according to the scanning; An image data path control circuit in a facsimile having a clock synchronizing clock for synchronizing with a scanning synchronizing clock and a clock generating means for generating a synchronizing printing clock for synchronizing image data during printing, wherein the generated image data is controlled by a predetermined control. A TPH 23 for printing in synchronization with a printing synchronization clock, a serial / parallel converter 24 for converting the generated image data into parallel image data in synchronization with the scanning synchronization clock, and the scanning synchronization clock. An eighth divider 26 for dividing and outputting the first DMA request signal and the parallel-converted image data according to the first DMA request signal. And a latch unit 25 for latching and outputting the latched image data on the data bus 201 by a predetermined transmission / reception DMA response signal, and connected to the data bus 201 and the communication lines L1 and L2. Simultaneously modulates the image data on the data bus 201 to analog signals and transmits them to the communication lines L1 and L2, and demodulates the analog signals when they are input through the communication lines L1 and L2. A modem 27 for generating a 2DMA request signal and outputting demodulated data on the data bus 201 by the transmission / reception DMA response signal; a memory 30 for storing image data on the data bus 201; And control the TPH 23 in the copy mode to control the system as a whole, and transmit / receive a DMA response signal through the inverter 32 in response to the first DMA request signal in the transmission mode. Is applied to the memory 30 The stored image data is coded and input to the modem 27, and in the reception mode, a transmission / reception DMA response signal is applied to the modem 27 in response to the second DMA request signal of the modem 27, and demodulation data is stored in the memory ( 30 and a data transceiver 29 connected between the data bus 201 and the CPU 28 for printing by controlling the TPH 23 after storing and decoding the same. It consists of a parallel / serial converter 31 which inputs image data stored in the memory 30 through the data bus 201 and converts it into serial data in synchronization with the printing synchronization clock and then applies the TPH 23 to the TPH 23. An image data path control circuit in a facsimile.

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