KR920007777Y1 - Memory access unit - Google Patents
Memory access unit Download PDFInfo
- Publication number
- KR920007777Y1 KR920007777Y1 KR2019870022630U KR870022630U KR920007777Y1 KR 920007777 Y1 KR920007777 Y1 KR 920007777Y1 KR 2019870022630 U KR2019870022630 U KR 2019870022630U KR 870022630 U KR870022630 U KR 870022630U KR 920007777 Y1 KR920007777 Y1 KR 920007777Y1
- Authority
- KR
- South Korea
- Prior art keywords
- signal
- flop
- flip
- input
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
Abstract
내용 없음.No content.
Description
제1도는 본 고안 장치에서의 파형도.1 is a waveform diagram of the device.
제2도 a-e는 본 고안 장치에서의 파형도.2 is a waveform diagram of the device of the present invention.
제3도는 종래 메모리 억세스 장치의 회로도.3 is a circuit diagram of a conventional memory access device.
제4도 a-e는 제3도 회로에서의 파형도.4 is a waveform diagram of a circuit of FIG.
본 고안은 퍼스날 컴퓨터의 메모리 억세스 장치에 관한 것으로서 특히 플립플롭을 설치하여 메모리의 RAS 신호를 연장시켜 제속 메모리를 사용하도록 한 메모리 억세스 장치에 관한 것이다.The present invention relates to a memory access device of a personal computer, and more particularly, to a memory access device in which a flip-flop is installed to extend a RAS signal of a memory to use a speed control memory.
종래의 메모리 억세스 장치는 제3도에 도시된 바와같이 메모리 기록신호()와 메모리 해독신호()에 반전기(31, 32)를 통하여 입력되는 OR 게이트(33)의 출력이 신호로서 그리고 신호(RAS)가 지연기(34)를 통과한 신호(CAS)가 각각 만들어 진다. 즉 제4도 a와 같은 클록 신호를 기준으로할때 제4도 a, b와 같은 메모리 기록신호()와 메모리 해독신호()가 OR게이트(33)에 반전기(31, 32)를 통하여 인가되면 OR게이트(33)의 출력에서는 제4도 d와 같은 신호(RAS)가 발생되고 이 신호(RAS)는 지연기(24)를 통하여 소정시간 지연되며, 메모리 기록신호()나 메모리 해독신호()의 기간내에서 데이타로서 제4도 e와같이 메모리를 억세스 하여야 하는데 메모리 억세스의 기능시간은 제4도 e와같이 145ns가 되므로 메모리까지의 지연기(24)의 지연시간으로 계산하면 120ns의 저속메모리는 억세스가 불가능하게 되는 단점이 있다.In the conventional memory access apparatus, as shown in FIG. ) And memory readout signal Is generated as an output of the OR gate 33 input through the inverters 31 and 32 as a signal, and a signal CAS whose signal RAS has passed through the delay unit 34, respectively. That is, when the clock signal shown in FIG. 4 is a reference to FIG. ) And memory readout signal Is applied to the OR gate 33 through the inverters 31 and 32, the signal RAS as shown in FIG. 4 d is generated at the output of the OR gate 33, and this signal RAS is a delay unit 24. Delayed by a predetermined time, and the memory write signal ( ) Or memory readout ( The memory must be accessed as shown in Fig. 4e as a data within the period of e.g., but the functional time of the memory access becomes 145ns as shown in Fig. 4e. The disadvantage is that access is not possible.
본 고안은 이러한 단점을 해결하기 위하여 NAMD게이트와 플립플롭을 설치하여 메모리의 RAS신호를 연장시켜 저속메모리의 억세스가 가능한 메모리 억세스장치를 제공하는 것을 목적으로 하여 이하 첨부된 도면을 참조하면서 본 고안 장치의 구성 및 작용효과를 설명하면 다음과 같다.The present invention has been made with reference to the accompanying drawings for the purpose of providing a memory access device that can access the low-speed memory by extending the RAS signal of the memory by installing a NAMD gate and a flip-flop to solve this disadvantage The composition and effect of the are described as follows.
제1도를 참조하면 본 고안 장치는 메모리 기록/해독신호(XMW/XMR)와 구동시작신호(ALE)가 입력되는 NAMD게이트(1)의 출력을 플립플롭(2)의 리세트단자(R)에 연결하고, 메모리 기록/해독신호(XMW/XMR)를 플립플롭(2)의 입력(D)에 연결함과 동시에 클릭신호(CLK)를 플립플롭(2)의 입력(CK)에 연결하며, 플립플롭(2)의 출력을 신호(RAS)로서 어드레스(A)가 입력되는 디코더(4)에 연결하고, 플립플롭(2)의 출력을 지연기(3)을 통하여 신호(CAS)로서 어드레서(A')가 입력되는 디코더(5)에 연결하여된 구성으로서 이러한 본 고안 장치의 작용효과는 제2도 a-e의 파형도를 참도하여 설명하면 메모리 기록/해독 버스 주기는 구동시작신호(ALE)의 하이가 되는 시점에서 시작되므로 제2도 b에서와 같은 구동시작신호(ALE)와 제2도 c와같은 메모리 기록/해독신호(XMW/XMR)를 NAMD게이트(1)에 입력시켜 플립플롭(2)을 리세트 시키면 제2도 d와같은 신호(RAS)가 발생된다.Referring to FIG. 1, the device of the present invention outputs the output of the NAMD gate 1 to which the memory write / read signal XMW / XMR and the driving start signal ALE are input, and the reset terminal R of the flip-flop 2. To the input (D) of the flip-flop (2) and the click signal (CLK) to the input (CK) of the flip-flop (2), The output of the flip-flop 2 is connected to the decoder 4 to which the address A is input as the signal RAS, and the output of the flip-flop 2 is addressed as the signal CAS through the delay unit 3. The operation and effect of the device of the present invention are explained by referring to the waveform diagram of FIG. 2 ae as a configuration connected to the decoder 5 to which (A ') is input. Since the drive start signal ALE as shown in FIG. 2B and the memory write / read signal XMW / XMR as shown in FIG. 2C are input to the NAMD gate 1, When resetting the flip-flop (2) it is also a second signal (RAS) occurs, such as d.
플립플롭(2)의 입력(CK)에는 제2도 a와같은 클록신호가 입력되므로 클록신호(T3)의 하강변까지의 시간이 240ns로 되어 150ns 및 200ns의 억세스 시간을 갖는 메모리도 대기신호 없이 사용이 가능하게 된다.Since the clock signal as shown in FIG. 2 is input to the input CK of the flip-flop 2, the time until the falling edge of the clock signal T 3 becomes 240 ns, and a memory having an access time of 150 ns and 200 ns is also a standby signal. It can be used without.
이상에서 설명된 바와같이 본 고안 장치에 의하면 신호(RAS)를 눌려주므로서 억세스 기간이 긴 저속 메모리도 대기 신호없이 메모리 기록 또는 메모리 해독이 가능하게 된다.As described above, according to the device of the present invention, even when the signal RAS is pressed, a low-speed memory having a long access period enables memory writing or memory decoding without a waiting signal.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019870022630U KR920007777Y1 (en) | 1987-12-22 | 1987-12-22 | Memory access unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019870022630U KR920007777Y1 (en) | 1987-12-22 | 1987-12-22 | Memory access unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR890014246U KR890014246U (en) | 1989-08-10 |
| KR920007777Y1 true KR920007777Y1 (en) | 1992-10-17 |
Family
ID=19270560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019870022630U Expired KR920007777Y1 (en) | 1987-12-22 | 1987-12-22 | Memory access unit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR920007777Y1 (en) |
-
1987
- 1987-12-22 KR KR2019870022630U patent/KR920007777Y1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| KR890014246U (en) | 1989-08-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5701417A (en) | Method and apparatus for providing initial instructions through a communications interface in a multiple computer system | |
| US4792929A (en) | Data processing system with extended memory access | |
| KR960004567B1 (en) | Output buffer of semiconductor memory device | |
| NO891581D0 (en) | PROCEDURE AND DEVICE FOR ACCESSING PAGE MODE MEMORY IN A COMPUTER SYSTEM. | |
| KR910001777A (en) | Speed memory line memory | |
| JPS5984289A (en) | Image signal output device | |
| KR920004946A (en) | VGA input / output port access circuit | |
| KR920007777Y1 (en) | Memory access unit | |
| KR970002679A (en) | Placement circuit for plug / play on PCI bus | |
| KR0184464B1 (en) | Decoding Circuit of Synchronous Semiconductor Memory Device | |
| KR900005442A (en) | Semiconductor memory | |
| JP2676725B2 (en) | Electronics | |
| KR900003527Y1 (en) | Dma circuit for ic used in data transmission and receiving | |
| KR930001217A (en) | Semiconductor memory | |
| KR100276263B1 (en) | Interface circuit for pc card | |
| KR940006830B1 (en) | Global memory control system for the scanner of pc/at | |
| RU1807522C (en) | Buffer storage | |
| KR970000140Y1 (en) | RTC interface circuit | |
| SU1387042A1 (en) | Buffer storage device | |
| JPS57130135A (en) | Timing control circuit | |
| SU1689964A1 (en) | The unit to interface a video controller and processor over a common bus | |
| JPH01105388A (en) | word line control circuit | |
| JPH04319597A (en) | Initialization circuit for storage circuit | |
| KR950003982A (en) | Method and system for providing data retention time by synchronous random access memory during write operation | |
| KR870003510A (en) | Memory connection state detection circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| UA0108 | Application for utility model registration |
Comment text: Application for Utility Model Registration Patent event code: UA01011R08D Patent event date: 19871222 |
|
| UG1501 | Laying open of application | ||
| A201 | Request for examination | ||
| UA0201 | Request for examination |
Patent event date: 19901025 Patent event code: UA02012R01D Comment text: Request for Examination of Application Patent event date: 19871222 Patent event code: UA02011R01I Comment text: Application for Utility Model Registration |
|
| UG1604 | Publication of application |
Patent event code: UG16041S01I Comment text: Decision on Publication of Application Patent event date: 19920921 |
|
| E701 | Decision to grant or registration of patent right | ||
| UE0701 | Decision of registration |
Patent event date: 19921230 Comment text: Decision to Grant Registration Patent event code: UE07011S01D |
|
| REGI | Registration of establishment | ||
| UR0701 | Registration of establishment |
Patent event date: 19930323 Patent event code: UR07011E01D Comment text: Registration of Establishment |
|
| UR1002 | Payment of registration fee |
Start annual number: 1 End annual number: 3 Payment date: 19930323 |
|
| UR1001 | Payment of annual fee |
Payment date: 19941227 Start annual number: 4 End annual number: 4 |
|
| UR1001 | Payment of annual fee |
Payment date: 19951226 Start annual number: 5 End annual number: 5 |
|
| UR1001 | Payment of annual fee |
Payment date: 19961230 Start annual number: 6 End annual number: 6 |
|
| UR1001 | Payment of annual fee |
Payment date: 19971229 Start annual number: 7 End annual number: 7 |
|
| UR1001 | Payment of annual fee |
Payment date: 19981221 Start annual number: 8 End annual number: 8 |
|
| FPAY | Annual fee payment |
Payment date: 20000930 Year of fee payment: 9 |
|
| UR1001 | Payment of annual fee |
Payment date: 20000930 Start annual number: 9 End annual number: 9 |
|
| LAPS | Lapse due to unpaid annual fee | ||
| UC1903 | Unpaid annual fee |