KR920007134A - 유전 패키지 본체에 전기도선이 있는 ic패키지 - Google Patents
유전 패키지 본체에 전기도선이 있는 ic패키지 Download PDFInfo
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- KR920007134A KR920007134A KR1019910016891A KR910016891A KR920007134A KR 920007134 A KR920007134 A KR 920007134A KR 1019910016891 A KR1019910016891 A KR 1019910016891A KR 910016891 A KR910016891 A KR 910016891A KR 920007134 A KR920007134 A KR 920007134A
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- annular portion
- conductor film
- dielectric
- dielectric annular
- package
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- 239000004020 conductor Substances 0.000 claims 22
- 239000004065 semiconductor Substances 0.000 claims 3
- 230000008054 signal transmission Effects 0.000 claims 1
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Abstract
Description
Claims (8)
- 반도체 칩 ; 반도체 칩을 싸기 위하여, 바닥부분, 바닥부분위에 배열되고 반도체 칩을 둘러싸는 제1유전 환상부분, 제1유전 환상부분위에 배열되는 제2유전 환성부분 및 제2유전 환상부분에 부착되는 캡부분으로 이루어지며, 상기 제1및 제2유전 환상부분은 상기 및 하부 표면, 내부 및 외부 가장자리와 내부 및 외부 가장자리 사이의 폭을 가지는 패키지 본체 ; 제2유전 환상부분의 폭보다 커서 제1유전 환상부분의 상부 표면의 제1부분이 제2유전 환상부분에 의해 덮혀지고 제1유전 환상부분의 상부 표면의 제2부분이 노출되도록 하는 제1유전 환상부분의 폭 ; 제1유전 환상부분의 내부 및 외부 가장자리 사이를 실제로 연장시키기 위해 제1유전 환상부분의 상부 표면상에 형성되는 전기도선 ; 제1유전 환상부분의 제1덮혀진 부분에 대응하여 제2도체막, 전기도선의 제1부분 및 제1도체막에 의해 스트립선을 형성하고, 제1유전 환상부분의 제2노출된 부분에 대응하여 전기도선의 제2부분 및 제1도체막에 의해 마이크로 스트립선을 형성하도록, 제1유전 환상부분의 하부 표면상에 접지 및 형성되어지는 제1도체막과, 제2유전 환상부분의 상기 표면상에 접지 및 형성되어지는 제2도체막 ; 및 최소한 제1유전 환상부분의 제2노출된 부분의 일부에 대응하여 제1유전 환상부분에 제공되고, 제1도체막보다 도선에 인접하고, 제1유전 혼상부분의 제2노광된 부분에 대응하여 전기도선의 제2부분으로 구성되는 접지되어지는 제3도체막으로 이루어진 IC패키지.
- 제1항에 있어서, 제1유전 환상부분이 서로 겹쳐지는 표면을 갖는 세분된 부분들로 이루어지고, 제3도체막이 겹쳐진 표면중의 하나에 형성되는 IC패키지.
- 제1항에 있어서, 제1유전 환상부분의 제1덮혀진 부분의 그의 내부와 외부 가장자리 사이에 위치하며, 제2노출된 부분은 제1덮혀진 부분의 안쪽위에 안부분과 제1덮혀진 부분의 바깥쪽에 위에 바깥부분으로 이루어지는 IC패키지.
- 제3항에 있어서, 제3도체막이 제1유전 환상부분의 제2노광된 부분의 안부분과 바깥부분에 대응하여 제공되는 IC패키지.
- 제3항에 있어서, 제3도체막이 제1유전 환상부분의 제2노광된 부분의 안부분과 바깥부분중의 하나에 대응하여 제공되는 IC패키지.
- 제1항에 있어서, 전기도선의 신호전송선과 최소한 하나의 전원선을 포함하고, 접지되어지는 제4좁은 도체막이 최소한 한 전원선에 대응하여 제1유전 환상부분에 제공되고 제3도체막에 연결되는 IC패키지.
- 제6항에 있어서, 접지되어지는 제5좁은 도체막이 최소한 한 전원선에다가 제4좁은 도체막에 대응하여 제2유전 환상부분에 제공되는 IC패키지.
- 제1항에 있어서, 제1유전 환상부분이 제2유전 환상부분의 두께와 같은 두께를 갖으므로 제1도체막 및 제2도체막이 전기도선으로 부터 같은 거리에 있게 되는 IC패키지.※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP90-259364 | 1990-09-28 | ||
JP2259364A JPH0766949B2 (ja) | 1990-09-28 | 1990-09-28 | Icパッケージ |
Publications (2)
Publication Number | Publication Date |
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KR920007134A true KR920007134A (ko) | 1992-04-28 |
KR950010107B1 KR950010107B1 (ko) | 1995-09-07 |
Family
ID=17333091
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910016891A KR950010107B1 (ko) | 1990-09-28 | 1991-09-27 | 유전 패키지 본체에 전기도선이 있는 ic 패키지 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5218230A (ko) |
EP (1) | EP0478160B1 (ko) |
JP (1) | JPH0766949B2 (ko) |
KR (1) | KR950010107B1 (ko) |
DE (1) | DE69123323T2 (ko) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0515508U (ja) * | 1991-07-31 | 1993-02-26 | 三菱電機株式会社 | マイクロ波用パツケージ |
US5184095A (en) * | 1991-07-31 | 1993-02-02 | Hughes Aircraft Company | Constant impedance transition between transmission structures of different dimensions |
JPH05190721A (ja) * | 1992-01-08 | 1993-07-30 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US5376909A (en) * | 1992-05-29 | 1994-12-27 | Texas Instruments Incorporated | Device packaging |
US5455385A (en) * | 1993-06-28 | 1995-10-03 | Harris Corporation | Multilayer LTCC tub architecture for hermetically sealing semiconductor die, external electrical access for which is provided by way of sidewall recesses |
GB2288286A (en) * | 1994-03-30 | 1995-10-11 | Plessey Semiconductors Ltd | Ball grid array arrangement |
JPH07288409A (ja) * | 1994-04-20 | 1995-10-31 | Nec Corp | マイクロ波集積回路装置 |
US5672911A (en) * | 1996-05-30 | 1997-09-30 | Lsi Logic Corporation | Apparatus to decouple core circuits power supply from input-output circuits power supply in a semiconductor device package |
US5691568A (en) * | 1996-05-31 | 1997-11-25 | Lsi Logic Corporation | Wire bondable package design with maxium electrical performance and minimum number of layers |
AU4902897A (en) | 1996-11-08 | 1998-05-29 | W.L. Gore & Associates, Inc. | Method for improving reliability of thin circuit substrates by increasing the T of the substrate |
US7336468B2 (en) | 1997-04-08 | 2008-02-26 | X2Y Attenuators, Llc | Arrangement for energy conditioning |
US9054094B2 (en) | 1997-04-08 | 2015-06-09 | X2Y Attenuators, Llc | Energy conditioning circuit arrangement for integrated circuit |
US7321485B2 (en) | 1997-04-08 | 2008-01-22 | X2Y Attenuators, Llc | Arrangement for energy conditioning |
KR100218368B1 (ko) * | 1997-04-18 | 1999-09-01 | 구본준 | 리드프레임과 그를 이용한 반도체 패키지 및 그의 제조방법 |
SE514425C2 (sv) * | 1999-06-17 | 2001-02-19 | Ericsson Telefon Ab L M | Övergång mellan stripline och mikrostrip i kavitet i flerlagers mönsterkort |
TW588532B (en) * | 2002-03-29 | 2004-05-21 | Realtek Semiconductor Corp | Management device and method of NAT/NAPT session |
US20040041254A1 (en) * | 2002-09-04 | 2004-03-04 | Lewis Long | Packaged microchip |
JP3938742B2 (ja) * | 2002-11-18 | 2007-06-27 | Necエレクトロニクス株式会社 | 電子部品装置及びその製造方法 |
KR100506738B1 (ko) * | 2003-11-03 | 2005-08-08 | 삼성전기주식회사 | 리크를 방지할 수 있는 세라믹 패키지 밀봉 구조, 리크를방지할 수 있는 세라믹 패키지 및 상기 세라믹 패키지의제조 방법 |
JP2008535207A (ja) | 2005-03-01 | 2008-08-28 | エックストゥーワイ アテニュエイターズ,エルエルシー | 共平面導体を有する調整器 |
JP5588419B2 (ja) * | 2011-10-26 | 2014-09-10 | 株式会社東芝 | パッケージ |
JP7005111B2 (ja) * | 2018-02-09 | 2022-01-21 | 矢崎総業株式会社 | 電子部品実装品 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0812887B2 (ja) * | 1985-04-13 | 1996-02-07 | 富士通株式会社 | 高速集積回路パツケ−ジ |
CA1320006C (en) * | 1986-06-02 | 1993-07-06 | Norio Hidaka | Package for integrated circuit |
JPH0793392B2 (ja) * | 1986-10-25 | 1995-10-09 | 新光電気工業株式会社 | 超高周波素子用パツケ−ジ |
US4922324A (en) * | 1987-01-20 | 1990-05-01 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device |
JPS63216366A (ja) * | 1987-03-05 | 1988-09-08 | Fujitsu Ltd | 集積回路用パツケ−ジ |
JP2580674B2 (ja) * | 1988-02-08 | 1997-02-12 | 三菱電機株式会社 | 高周波用モールド型パッケージ |
JPH081918B2 (ja) * | 1989-04-28 | 1996-01-10 | 日本電気株式会社 | 超高周波帯実装構造 |
-
1990
- 1990-09-28 JP JP2259364A patent/JPH0766949B2/ja not_active Expired - Fee Related
-
1991
- 1991-08-28 US US07/751,094 patent/US5218230A/en not_active Expired - Lifetime
- 1991-09-04 DE DE69123323T patent/DE69123323T2/de not_active Expired - Fee Related
- 1991-09-04 EP EP91308078A patent/EP0478160B1/en not_active Expired - Lifetime
- 1991-09-27 KR KR1019910016891A patent/KR950010107B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0478160A2 (en) | 1992-04-01 |
US5218230A (en) | 1993-06-08 |
JPH0766949B2 (ja) | 1995-07-19 |
EP0478160B1 (en) | 1996-11-27 |
EP0478160A3 (en) | 1993-03-31 |
JPH04137655A (ja) | 1992-05-12 |
DE69123323T2 (de) | 1997-04-03 |
KR950010107B1 (ko) | 1995-09-07 |
DE69123323D1 (de) | 1997-01-09 |
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