KR920004923B1 - Semiconductor integrated circuit device - Google Patents

Abstract

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Description

Semiconductor integrated circuit device

1 is a conventional inverter circuit diagram.

2A and 2B are two input NOR circuit diagrams of the prior art.

3 is an inverter circuit diagram according to a first embodiment of the present invention.

4 is a schematic cross-sectional view showing a second embodiment of the present invention in the case where the inverter circuit of FIG. 3 is integrated on a semiconductor substrate.

5 is a two-input NAND circuit diagram according to a third embodiment of the present invention.

6 is a two-input NOR circuit diagram according to a fourth embodiment of the present invention.

7 is a latch circuit diagram according to a fifth embodiment of the present invention.

8 is an inverter circuit diagram according to a sixth embodiment of the present invention.

9 is a two-input NAND circuit diagram according to a seventh embodiment of the present invention.

10 is a NOR circuit diagram according to an eighth embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuit devices, and more particularly, to semiconductor integrated circuit devices in which field effect transistors (FETs) and bipolar transistors (BiFETs) are combined.

For example, an inverter circuit as shown in FIG. 1 is known as a gate circuit which combines a field effect transistor and a bipolar transistor to achieve high speed and low power consumption (Japanese Patent Laid-Open No. 54-148469).

The inverter circuit includes a P-type insulated gate field effect transistor (hereinafter referred to as PMOS) 50, an N-type insulated gate field effect transistor (hereinafter referred to as NMOS) 51, an NPN transistor (hereinafter referred to as NPN) 53, A PNP transistor (hereinafter referred to as PNP) 54 is formed. In this circuit, when the input 55 is at the " 0 " level, the PMOS 50 is turned on and the NMOS 51 is turned off. As a result, the base potentials of the NPN 53 and the PNP 54 rise, and the NPN 53 is turned on and the PNP 54 is turned off, so that the output 56 is at " 1 " level. When the input 55 is at the " 1 " level, the PMOS 50 is turned off and the NMOS 51 is turned on. Therefore, since the base potentials of the NPN 53 and the PNP 54 are lowered, the NPN 53 is turned off, the PNP 54 is turned on, and the output 56 is at " 0 " level. However, for example, when the NPN 53 is turned on and the output 56 is at " 1 " level, the output 56 does not fully rise to the power supply potential and only rises up to the power supply potential -VBE. However, VBE is a forward voltage between base emitters of the NPN 53. For this reason, the logic gate of the next stage does not turn off completely, and DC current may flow to the logic gate of the next stage. In addition, since no power supply voltage is applied between the gate sources of the NMOS gate of the next logic gate, the on-resistance of the NMOS of the logic gate of the next stage is increased so that the high speed of the logic gate of the next stage is not prevented. .

In addition, a two-input NOR gate circuit as shown in FIG. 2A is also known (see, for example, IEEE Trans. Electron Devices, Vol, ED-16, No. 11, pp. 945-951, Nov, 1969). This is a combination of NPNs 301 and 302 with a C-MOS transistor NOR gate circuit composed of PMOSs 200 and 201 and NMOSs 202 and 203 shown in FIG. In the case where the NPNs 301 and 302 are turned off, there is no means for forcibly releasing the accumulated small charges, so that the time for turning one NPN 301 and 302 off becomes longer. For this reason, the state in which the first and second NPNs 301 and 302 are both turned on for a long time not only increases power consumption but also slows down the switching time. Further, for example, when the NPN 301 is turned on and the output is at " 1 " level, the output level does not completely rise to the power supply voltage as in the first diagram, and there is a similar problem.

In addition, examples of the device structure of the bipolar MOS composite are described in IEEE Transaction on Electron Devies, Vol. ED-16, No. 11, 1969 to P.946. However, since one bipolar transistor is a vertical bipolar transistor whose collector is an N-type substrate, the collector resistance is high and not high performance. In addition, since another bipolar transistor is horizontal, the parasitic capacitance is large and similarly not high performance. Therefore, even if a bipolar MOS composite circuit is constructed using these bipolar devices, a high speed circuit cannot be obtained. In addition, another bipolar MOS composite device structure example is disclosed in Japanese Patent Laid-Open No. 56-100461. In the vertical bipolar transistor separated from the P-type substrate and in the PMOS portion, the base and the drain of the PMOS overlap. In the NMOS section, the base also serves as the P well of the NMOS. Therefore, when a bipolar MOS composite circuit is formed using these devices, even though the latch up phenomenon occurs in the PMOS section, for example, the NMOS section has a large capacity between the base and the collector of the bipolar transistor, so that a high speed circuit cannot be obtained. As described above, in the conventional bipolar MOS composite device structure, a high speed and high reliability bipolar MOS composite circuit cannot be obtained.

In addition, the device arrangement of the inverter of the bipolar MOS composite is IEEEE Transaction Electron Devices, Vol. ED-16, No. 11, 1969 to P.946. However, this element arrangement example is a layout of a circuit without an emitting element of a bipolar transistor; The drawback was that the power consumption was large and not practical.

SUMMARY OF THE INVENTION An object of the present invention is to compensate for the shortcomings of the CMOS circuit and the bipolar transistor circuit described above, and to provide a high speed and low power consumption semiconductor integrated circuit device composed of a field effect transistor and a bipolar transistor.

Another object of the present invention is to provide a device structure capable of realizing a high speed and high reliability bipolar MOS composite circuit.

It is still another object of the present invention to provide a device arrangement method of a low power consumption and high density bipolar MOS composite circuit including the emission element of a bipolar transistor.

It is still another object of the present invention to provide a high speed, low power consumption, high density, high reliability bipolar MOS composite LSI, which compensates for the drawbacks of the MOS LSI, bipolar LSI, and bipolar MOS composite device described above.

In order to achieve the above object, in a bipolar MOS composite circuit comprising an output stage consisting of a bipolar transistor, a logic driving circuit and driving a bipolar transistor at the same time, when the bipolar transistor is turned off, A pull-up means is provided between the base emitters of the bipolar transistor so that the output signal rises up to the power supply potential while providing an element for emitting accumulated charge.

In the BiMOS device which forms an output stage with a bipolar transistor, adopts logic as a MOS transistor, and forms a circuit which drives a bipolar transistor to achieve the above object, a bipolar transistor is formed from a P-type substrate. It is separated vertically, and the base region is separated from the drain and source regions of the MOS. The vertical type refers to a type in which the essential operating parts of the emitter, base, and collector are arranged in the vertical direction.

The first bipolar transistor at the top and the second bipolar transistor at the bottom constitute a totem pole output stage, and include a first field effect transistor between the base and the collector of the first bipolar transistor and a base between the base and the collector of the second bipolar transistor. The CMOS transistor of the field effect transistor adopts logic and constitutes a circuit for driving the bipolar transistor, the first charge releasing means connected to the base of the first bipolar transistor and the second connected to the base of the second bipolar transistor. In a BiMOS device forming a bipolar CMOS composite circuit having charge releasing means, the distance between the first bipolar transistor and the first field effect transistor is shorter than the distance between the first bipolar transistor and the second field effect transistor, and the second Bipolar Transistors and Second Field Effect The distance between the first bipolar transistor and the first charge releasing means is shorter than the distance between the transistor, and the distance between the first bipolar transistor and the second charge releasing means is greater than the distance between the second bipolar transistor and the first charge releasing means. It is short.

In a bipolar MOS composite circuit in which an output stage is constituted by a bipolar transistor, a logic is adopted as a MOS transistor, and a circuit for driving a bipolar transistor is provided, an element for releasing accumulated charge from the transistor when the bipolar transistor is turned off is provided. As a result, the bipolar transistor can be turned off quickly and the through current can be reduced, resulting in a high speed, low power consumption bipolar MOS composite circuit. In addition, by providing pull-up means between the base emitters of the bipolar transistors, the output level can be raised to the power supply voltage completely, and the logic gates of the next stage can contribute to lower power and higher speed.

In a BiMOS device in which an output stage is constituted by a bipolar transistor, a logic is employed as a MOS transistor, and a bipolar MOS composite circuit is formed, which is a circuit for driving a bipolar transistor, the bipolar transistor is a vertical type separated from a P-type substrate. By separating the base region from the drain and source regions of the MOS, since the bipolar transistor is a vertical type separated from the P-type substrate, a high performance bipolar transistor is obtained, and high-speed circuit operation is possible. In addition, since the base region of the bipolar transistor is separated from the drain and source regions of the MOS, the latchup phenomenon can be easily countermeasured. Therefore, a high speed, low power consumption, and high reliability bipolar MOS composite LSI can be obtained.

The first bipolar transistor at the top and the second bipolar transistor at the bottom constitute a totem pole output stage, and the first field effect transistor between the base and the collector of the first bipolar transistor and the second between the base and the collector of the second bipolar transistor. The CMOS transistor of the field effect transistor adopts logic and constitutes a circuit for driving the bipolar transistor, the first charge emitting means connected to the base of the first bipolar transistor and the second charge connected to the base of the second bipolar transistor. In a BiMOS device forming a bipolar CMOS composite circuit having emitting means, the distance between the first bipolar transistor and the first field effect transistor is shorter than the distance between the first bipolar transistor and the second field effect transistor, and the second bipolar device is formed. Transistor and Second Field Effect Transistor The distance between the stator is shorter than the distance between the second bipolar transistor and the first field effect transistor, and the distance between the first bipolar transistor and the first charge-emitting means is greater than the distance between the first bipolar transistor and the second charge-emitting means. By shorting the distance between the second bipolar transistor and the second charge releasing means to be shorter than the distance between the second bipolar transistor and the first charge releasing means, the bipolar CMOS composite circuit can be mounted on a semiconductor substrate with high density. . Therefore, a high speed, low power consumption, and high density bipolar MOS composite LSI can be obtained.

Other objects and features of the present invention will become apparent from the following description of the embodiments.

Next, this invention is demonstrated concretely based on an Example.

3 shows an inverter circuit as a first embodiment of the present invention.

In FIG. 3, reference numeral 14 denotes a first NPN bipolar transistor (hereinafter referred to as a first NPN) in which the collector C is connected to the power supply terminal 1 having the first fixed potential and the emitter E is connected to the output terminal 17. 15 is a second NPN bipolar transistor (hereinafter referred to as a second NPN) in which the collector C is connected to the output terminal 17 and the emitter E is connected to the ground potential GND which is the second fixed potential. ), 10, P-type insulated gate field effect transistor having a gate (G) connected to the input terminal (16) and a source (S) and a drain (D) connected to the collector (C) and the base (B) of the first NPN, respectively. (Hereinafter referred to as PMOS), 11 denotes an N-type insulation in which a gate G is connected to the input terminal 16 and a drain D and a source S are connected to the collector C and the base B of the second NPN. A gate field effect transistor (hereinafter referred to as NMOS), 12 is a resistor connecting the drain D of the PMOS 10 and the drain D of the NMOS 11D, and 13 is the base of the second NPN 15. (B) and emitter (E) It is a resistor to be connected.

4 is a schematic cross-sectional view when the inverter circuit shown in FIG. 3 is integrated on a semiconductor substrate.

The PMOS 10, the first NPN 14, the resistors 12 and 13 and the NMOS 11 are formed in the isolation 212 of the semiconductor substrate 210, and the second NP 15 is disposed in the isolation 213. Configure. 227 is a buried layer. The P ⁺ region 219 and the PMOS (10) to the gate electrode (G) is configured, NMOS (11) to the N ⁺ region 223 and the gate electrode (G) in the P-well 214 it is formed. The first NPN 14 uses the p region 217 as the base b, the N ⁺ region 218 in the P region 217 as the emitter E, and the N ⁺ region 215 as the collector ( C). The second NPN 15 uses the P region 225 in the isorace 213 as the base B, the N ⁺ region 226 in the P region 225 as the emitter E, and the N ^{The +} region 224 is set as the collector C.

Table 1 shows the logic operation of FIG. 3 of this embodiment.

TABLE 1

When the input 16 is at the " 0 " level, the PMOS 10 is turned on and the NMOS 11 is turned off. Therefore, the first NPN 14 is turned on. At this time, since the NMOS 11 is turned off, supply of current to the second NPN 15 is stopped, and accumulated charges accumulated in the base B and the NMOS 11 of the second NPN 15 are released. 2NPN 15 is rapidly turned off. Therefore, the emitter current of the first NPN 14 charges the load so that the output 17 rapidly becomes " 1 " level.

When the input 16 is at the " 1 " level, the PMOS 10 is turned off and the NMOS 11 is turned on. At this time, since the PMOS 10 is turned off, the supply of current to the first NPN 14 is stopped, and the accumulated charge accumulated in the base B and the PMOS 10 of the first NPN 14 is resisted. The first NPN 14 is rapidly turned off because it is emitted via In addition, since the NMOS 11 is turned on and the drain D and the source S are short-circuited, the base B of the second NPN 15 has a current from the output 17 as described above. Since the current of accumulated charge accumulated in the base B and the PMOS 10 of the first NPN 14 is supplied together, the NPN 15 is rapidly turned on. Therefore, the output 17 rapidly goes to the "0" level.

Here, the action of the resistor 12 will be described again. As described above, the resistor 12 accumulates in the base B of the PMOS 10 and the first NPN 14 when the PMOS 10 and the first NPN 14 are switched from on to off. To rapidly turn off the first NPN 14 by emitting the light, and to supply the released charge to the base B of the second NPN via the turned on NMOS 11 to rapidly turn on the second NPN. Has

In addition, since the resistor 12 is provided between the drain D of the PMOS 10 and the drain D of the NMOS 11, a conductive path does not occur between the power supply terminal 1 and GND, thereby reducing the power consumption. Can be achieved. That is, when the resistor 12 is installed to be connected to the drain of the PMOS 10 and GND, when the input 16 is at " 0 " level, a conductive path is generated between the power supply terminal 1 and GND. As a result, the power consumption increases, but in this embodiment, no conductive path is generated. In this embodiment, the resistor 12 is also connected to the output 17, so that when the input 16 is at the " 0 " level, the output 17 is transmitted through the PMOS 10 and the resistor 12 (potential transfer means). ) Can be raised to the potential of the power supply terminal 1, so that a sufficient noise margin can be secured. In addition, since the PMOS of the logic gate of the next stage is completely turned off, DC current does not flow to the logic gate of the next stage, contributing to lower power consumption. In addition, since the power supply voltage is applied between the gate and the source of the NMOS gate of the logic gate of the next stage, the on-resistance of the NMOS of the logic gate of the next stage becomes small, contributing to the higher speed of the logic gate of the next stage.

Next, the action of the resistor 13 will be described again. As described above, the resistor 13 has accumulated charge accumulated in the base B of the NMOS 11 and the second NPN 15 when the NMOS 11 and the NPN 15 are switched from on to off. To release the second NPN 15 rapidly. In the present embodiment, when the input 16 is at the "1" level, the output 17 can be lowered to the "0" level via the resistor 13 and the N transistor 11, so that a sufficient noise margin can be secured. Can be. In addition, the same effect as described above is obtained at the next logical gate.

In addition, in the present embodiment, since the bipolar transistor uses only the NPN transistor, it is easy to match the switching characteristics.

In addition, it can be easily understood that the portion composed of the NMOS 11, the bipolar transistor 15, and the resistor 13 can be regarded as a pull-down circuit or switching means in a logic circuit.

In this embodiment of FIG. 4, a vertical type high performance bipolar transistor in which the bipolar transistors 14 and 15 constituting the bipolar MOS composite circuit are separated from the P substrate 210 is obtained, thereby enabling high-speed circuit operation. In addition, since the base regions 217 and 225 are separated into the drain source regions 219 and 223 of the bipolar, the latch-up phenomenon can be easily countermeasured.

Further, the distance between the first bipolar transistor 14 and the first field effect transistor 10 constituting the bipolar MOS composite circuit is shorter than the distance between the first bipolar transistor 14 and the second field effect transistor 11, The distance between the second bipolar transistor 15 and the second field effect transistor 11 is shorter than the distance between the second bipolar transistor 15 and the first field effect transistor 10, and the first bipolar transistor 14 The distance between the first charge releasing means 12 is shorter than the distance between the first bipolar transistor 14 and the second charge releasing means 13, and the first bipolar transistor 15 and the second charge releasing means 13 Since the distance between the first bipolar transistor 15 and the first charge releasing means 12 is made shorter, the bipolar MOS composite circuit can be efficiently mounted on the semiconductor substrate with high density. Therefore, the present embodiment can realize a high speed, low power consumption, high density, and high reliability bipolar MOS composite LSI.

In this embodiment, since the P well 214 of the NMOS 11 is separated from the P-type substrate 210, the potential of the P well 214 can be set independently of the potential of the P-type substrate 210. have. Therefore, when the ECL (Emit ter Coupled Logic) and TTL (Transistor Transistor Logic) are mixed, there is an effect of increasing the degree of freedom in design.

5 is a two-input NAND circuit as a third embodiment of the present invention. In Fig. 5, reference numeral 26 denotes a first NPN in which collector C is connected to power supply terminal 1 and emitter E is connected to output terminal 29, while collector C is output terminal 29. 2 NPN, 28 is connected to the ground potential (GND), two input terminals, and 20 and 21 are each gate (G) is connected to the other input terminal 28 and each PMOS, 22 and 23, in which the source S and each drain D are connected in parallel between the collector C and the base B of the first NPN 26, respectively, have different gates G, respectively. NMOS 24 connected to the terminal 28 and each drain D and each source S are connected in series between the collector C and the base B of the second NPN 27 are respectively PMOS 20. 2 1) is a resistor for connecting the drain D of the NMOS 22 and the drain D of the NMOS 22, and 25 is a resistor for connecting the base B and the emitter E of the second NPN 27.

Table 2 shows the basic operation of this embodiment.

TABLE 2

First, when either side of the input 28 is at the " 0 " level, one of the PMOSs 20 and 21 is turned on, and one of the NM OSs 22 and 23 is turned off. Therefore, the base potential of the first NPN 26 is increased to turn on the first NPN 26. At this time, either one of the NMOSs 22 and 23 is turned off, so that the current to the second NPN 27 is stopped and at the same time, accumulated in the base B and the NMOSs 22 and 23 of the second NPN 27. Since the accumulated charge is released, the second NPN 27 is rapidly turned off. Therefore, the emitter current of the first NPN 26 charges the load, so that the output 29 quickly becomes the " 1 " level.

When both of the inputs 28 are at the " 0 " level, both of the PMOSs 20 and 21 are turned on, and both of the NMOSs 22 and 23 are turned off. Therefore, the operation becomes the same as above and the output 29 becomes "1". On the other hand, when both of the inputs 28 are at the " 1 " level, both of the PMOSs 20 and 21 are turned off, and both of the MMOSs 22 and 23 are turned on. At this time, since both of the PMOSs 20 and 21 are turned off, the supply of current to the first NPN 26 is stopped and at the same time, the accumulated charge accumulated in the base B and the PMOSs 20 and 21 of the first NPN 26. Is emitted, the first NPN 26 is rapidly turned off.

In addition, since the NMOSs 22 and 23 are turned on and a short circuit between the drain D and the source S, the base B of the second NPN 27 has a current from the output 29, and As described above, the base B and the PMOS 27 of the first NPN 26 are rapidly turned on. Therefore, the output 29 rapidly goes to the "0" level.

Also in this embodiment, the same effects as in the first embodiment can be expected. It will be readily understood that the portion consisting of the NMOS 22, 23, bipolar transistor 27, and resistor 25 can be regarded as a pull-down circuit or switching means in a logic circuit.

In the present embodiment, a two-input NAND circuit has been described as an example, but the present invention can also be applied to a general K-input NAND circuit (K? 2) such as three-input NAND and four-input NAND.

6 is a two-input NOR circuit as a fourth embodiment of the present invention.

In Fig. 6, reference numeral 36 denotes a first NPN in which collector C is connected to power supply terminal 1 and emitter E is connected to output terminal 39, and 37, collector C is output terminal 39. In FIG. 2 NPN, 38 connected to ground potential GND, and 2 input terminals, 30 and 31, each gate G connected to a different input terminal 38, PMOSs 32 and 33, in which the source S and each drain D are connected in series between the collector C and the base B of the first NPN 36, respectively, have different gates G, respectively. NMOS and 34 are connected to the terminal 38 and each drain D and the source S are connected in parallel between the collector C and the base B of the second NPN 37 respectively, and the PMOS 31 The resistor D connects the drain D of the transistor to the drain D of the NMOS 32, 33, and the resistor 35 connects the base B of the NPN 37 and the emitter E to each other.

Table 3 shows the logic operation of this embodiment.

TABLE 3

First, when both of the histories 38 are at the " 0 " level, both of the PMOSs 30 and 31 are turned on, and both of the NMOSs 32 and 33 are turned off. Therefore, the base potential of the first NPN 36 rises and the first NPN 36 turns on.

At this time, both of the NMOSs 32 and 33 are turned off, the supply of current to the first NPN 37 is stopped, and the accumulated charge accumulated in the base B and the NMOSs 32 and 33 of the second NPN 37. Is emitted, the second NPN 37 is rapidly turned off. Therefore, the emitter current of the first NPN 36 charges the load, so that the output 39 quickly becomes " 1 " level.

When either of the inputs 38 is at the " 1 " level, one of the PMOSs 30 and 31 is turned off, and either of the NMOSs 32 and 33 is turned on. At this time, since either of the PMOSs 30 and 31 is turned off, the supply of the current to the first NPN 36 is stopped, and any of the base B and the PMOSs 30 and 31 of the first NPN 36 is stopped. Since the accumulated charge accumulated on one side is released, the first NPN 36 is rapidly turned off. In addition, since either of the NMOSs 32 and 33 is turned on, and the drain D and the source S are short-circuited, the base B of the second NPN 37 is connected to the base B from the output 39. Since the current and the accumulated charge current supplied to either the base B of the first NPN 36 or the PMOSs 30 and 31 as described above are supplied together, the second NPN 37 is rapidly turned on. . Therefore, the output 39 quickly goes to the "0" level.

When both of the inputs 38 are at the " 1 " level, both of the PMOSs 30 and 31 are turned off, and both of the NMOSs 32 and 33 are turned on. The operation is thus the same as above and the output 39 is at " 0 " level.

Also in this embodiment, the same effects as in the first embodiment can be achieved. It will be readily understood that the portion consisting of the NMOSs 32 and 33, the bipolar transistor 37 and the resistor 35 can be regarded as a pull-down circuit or switching means in a logic circuit.

In the present embodiment, a two-input NOR circuit has been described as an example, but the present invention can also be applied to general K-input NOR circuits K2 such as three-input NOR and four-input NOR.

FIG. 7 shows a latch using the inverter circuit shown in FIG. 3 at an output section which is a fifth embodiment of the present invention.

In FIG. 7, 42 is a CMOS inverter for inverting the latch pulse 401, 40 is a transfer gate for transmitting the data input 400, 43 is a CMOS inverter constituting a storage unit, 41 is a transfer gate, and a third The same reference numerals denote the same and equivalents. When latching the data input 400, the latch pulse 401 is set to "1". Then, the transfer gate 40 is turned on and the transfer gate 41 is turned off to write data. After that, when the ratchet pulse 401 is set to "0", the transfer gate 40 is turned off and the transfer gate 41 is turned on. Therefore, data is retained in the inverter 43, the BiMOS hybrid inverter, and the transfer gate 41.

According to this embodiment, a circuit system of driving a BiMOS circuit or a CMOS circuit with a BiMOS circuit is realized by a latch circuit and a CMOS circuit having a minimum configuration of two stages of a CMOS driving stage and a bipolar output stage, thereby enabling high speed, low power consumption, and high density LSI. do.

8 is an inverter circuit as a sixth embodiment of the present invention.

In FIG. 8, 114 denotes a first PNP bipolar transistor (hereinafter referred to as first) in which emitter E is connected to power supply terminal 1 having a first fixed potential, and collector C is connected to output terminal 17. In FIG. 115 is a second PNP bipolar transistor (hereinafter referred to as a second PNP) in which the emitter E is connected to the output terminal 17 and the collector C is connected to a ground potential GND having a second fixed potential. And 10 are PMOSs in which the gate G is connected to the input terminal 16 and the source S and the drain D are connected to the base B and the collector C of the first NPN 114, respectively. NMOS, whose gate G is connected to the input terminal 16 and the drain D and the source S are connected to the base B and collector C of the second PNP 115, 12 is the PMOS 10 Resistor (potential transfer means) for connecting the drain (D) of the N2 and the drain (D) of the NMOS 11, 13 is a resistor for connecting the emitter (E) to the base (B) of the first NPN (114). .

This embodiment is an embodiment in which the NPN bipolar transistors 14 and 15 in the first embodiment shown in FIG. 3 are replaced with the PNP bipolar transistors 114 and 115, and operate in the same manner as in the first embodiment. In addition, it can be easily understood that the portion consisting of the PMOS 10, the bipolar transistor 114, and the resistor 13 can be regarded as a pull-up circuit or switching means in a logic circuit.

9 is a two-input NAND circuit diagram according to the seventh embodiment of the present invention.

In FIG. 9, reference numeral 326 denotes PNP, in which the emitter E is connected to the power supply terminal 1 and the collector C is connected to the output terminal 29, and the emitter E is connected to the output terminal 29. Second PNP, 28 connected to the ground power supply GND, and the collector C is connected to the ground power supply GND. In the PMOSs 22 and 23 where S and the angle D are connected in parallel between the base B of the first PNP 326 and the collector C, respectively, input terminals having different gates G are respectively. NMOS, 24 connected to (28) and each drain (D) and each source (S) connected in series between the base (B) and the collector (C) of the second PNP 327, respectively, PMOS (20, A resistor for connecting the drain D of the 21 and the drain D of the NMOS 22, 25 is a resistor for connecting the base B and the emitter E of the first PNP 326.

This embodiment is an embodiment in which the NPN bipolar transistors 26 and 27 in the third embodiment shown in FIG. 5 are replaced with PNP bipolar transistors 326 and 327. The same operation as that in the third embodiment is performed. It will be readily understood that the portion consisting of the PM OS 20, 21, the bipolar transistor 326, and the resistor 25 can be regarded as a pull-up circuit or switching means in a logic circuit.

In the present embodiment, a two-input NAND circuit has been described as an example, but the present invention can also be applied to a general K-input NAND circuit (K? 2) such as three-input NAND and four-input NAND.

10 is a two-input NOR circuit as an eighth embodiment of the present invention.

In FIG. 10, 436 is the first PNP in which the emitter E is connected to the power supply terminal 1 and the collector C is connected to the output terminal 39, and 437 is the emitter E in the output terminal ( 2) PNP, 38 connected to 39) and collector C connected to ground potential GND, 38 having two input terminals, 30 and 31 having their respective gates G connected to different input terminals 38, PMOSs 32 and 33, in which the source S and the angular drain D are connected in series between the base B of the first PNP 436 and the collector C, respectively, have different gates G, respectively. NMOS and 34 are connected to the terminal 38 and each drain D and each source S are connected in parallel between the base B of the second NPN 437 and the collector C in parallel, respectively. Is a resistor that connects the drain D of the ()) and the drains (D) of the NMOSs (32, 33), and 35 is a resistor that connects the base (B) and the emitter (E) of the first PNP (436).

This embodiment is an embodiment in which the NPN bipolar transistors 36 and 37 in the fourth embodiment shown in FIG. 6 are replaced with PNP bipolar transistors 436 and 437, and operate in the same manner as in the fourth embodiment. It will be readily understood that the portion consisting of the PMOS 30, 31, the bipolar transistor 436, and the resistor 25 can be regarded as a pull-up circuit or switching means in a logic circuit.

In the present embodiment, a two-input NOR circuit has been described as an example, but the present invention can also be applied to a general K-input NOR circuit (K? 2) such as a three-input NOR or a four-input NOR.

In addition, it is very easy for a person skilled in the art to modify the sixth, seventh and eighth embodiments as in the fifth embodiment shown in FIG.

In the embodiment of the present invention, only the NAND circuit and the NOR circuit are described as the logic gates. However, when the logic gate circuits of the CMOS transistors are connected in combination with the front ends of the circuits, the AND circuit, the OR circuit, and the like are connected. It is also very easy to think of other logic gate circuits, a combinational logic circuit, a sequence logic circuit such as a flip-flop, a shift register, and the like.

As described above, according to the present invention, a high speed and low power consumption gate circuit including a field effect transistor and a bipolar transistor can be obtained.

In addition, according to the present invention, since the bipolar MOS composite circuit is formed by separating the base region from the source and drain regions of the MOS using a vertical bipolar transistor separated from the substrate, the bipolar MOS composite circuit has high speed, low power consumption, and high reliability. MOS composite LSI can be realized.

In addition, according to the present invention, since the device constituting the bipolar MOS composite circuit is mounted in an optimal arrangement, a high speed, low power consumption, and high density bipolar MOS composite LSI can be realized.

Claims (12)

A first bipolar transistor having a collector of a first conductivity type connected to a first potential, an emitter of a first conductivity type connected to an output terminal, and a base of a second conductivity type; A first field effect transistor connected between the base and the collector of the first bipolar transistor; Potential transfer means connected between the base and the emitter of the first bipolar transistor; And switching means connected between the output terminal and the second potential, wherein the gate and the switching means of the first field effect transistor are connected to an input terminal. 2. The semiconductor integrated circuit device according to claim 1, wherein said first field effect transistor is of a second conductivity type. The semiconductor integrated circuit according to claim 1, wherein said potential transfer means is made of a resistor. The switching device of claim 1, wherein the switching means is turned on when the first bipolar transistor is turned off, and the switching means is turned off when the first bipolar transistor is turned on. A semiconductor integrated circuit device, characterized by operating complementarily. A first bipolar transistor having a collector of a first conductivity type connected to a first potential, an emitter of a first conductivity type connected to an output terminal, and a base of a second conductivity type; A first field effect transistor connected between the base and the collector of the first bipolar transistor; Potential transfer means connected between the base and the emitter of the first bipolar transistor; Switching means connected between said output terminal and a second potential; And a feedback means connected between the output terminal and the input terminal, wherein a gate of the first field effect transistor and the switching means are connected to the input terminal. A first bipolar transistor having a collector of a first conductivity type connected to a first potential, an emitter of a first conductivity type connected to an output terminal, and a base of a second conductivity type; A first field effect transistor connected between the base and the collector of the first bipolar transistor; Potential transfer means connected between the base and the emitter of the first bipolar transistor; Switching means connected between said output terminal and a second potential; And a CMOS circuit for outputting an output signal to an input terminal, wherein a gate of the first field effect transistor and the switching means are connected to the input terminal. A bipolar FET device having an output stage including a bipolar transistor and an input stage including a field effect transistor (FET) that adopts logic and drives a bipolar transistor, wherein the bipolar transistor is vertical and separated from a substrate and has a base region. And a source and a drain region of the FET. 8. The semiconductor integrated circuit device according to claim 7, wherein the bipolar transistor is an NPN bipolar transistor, the substrate is a P-type substrate, and the FET is a MOS transistor. A bipolar CMOS composite device comprising a P-type substrate including a bipolar transistor and a CMOS transistor, wherein the P wells of the NMOS are separated from the P-type substrate. A bipolar output circuit comprising first and second bipolar transistors of the same conductivity type in which collector emitter current paths are connected in series with each other; At least one field effect transistor that receives an input signal and sends a first signal to a base of the first bipolar transistor to control an on-off state of the first bipolar transistor; and a first signal to send a second signal to the base of the second bipolar transistor. A driving circuit comprising means for controlling an on off state of a second bipolar transistor in complementary relationship with an on off state of the transistor; Base charge releasing means of the first and second bipolar transistors, wherein the first and second bipolar transistors are separated from the first conductive semiconductor substrate and are separated from each other in the second conductive semiconductor region. A vertically shaped semiconductor integrated circuit device, characterized in that the base regions of the first and second bipolar transistors are separated into source and drain regions of the field effect transistor. The first bipolar transistor at the top and the second bipolar transistor at the bottom constitute a totem-pool output stage, and between the base and the collector of the first field effect transistor (FET) and the second bipolar transistor between the base and the collector of the first bipolar transistor. Complementary logic EFT (CF ET) of the second field effect transistor and a circuit for driving the bipolar transistor, the circuit of the first charge-emitting means and the second bipolar transistor connected to the base of the first bipolar transistor In a BiFET device forming a bipolar CFET composite circuit having a second charge-emitting means connected to a base, the distance between the first bipolar transistor and the first field effect transistor is between the first bipolar transistor and the second field effect transistor. Shorter than the distance, the second bipolar transistor and the second field effect transistor The distance between the second bipolar transistor and the first field effect transistor is shorter than that of the ster, and the distance between the first bipolar transistor and the first charge-emitting means is equal to the second charge-emitting means of the first bipolar transistor. And a distance between the second bipolar transistor and the second charge releasing means is shorter than a distance between the second bipolar transistor and the second charge releasing means. 12. The semiconductor integrated circuit device according to claim 11, wherein the bipolar transistor is an NPN bipolar transistor, and the FET is a MOS transistor.