KR920003398B1 - Motion adaptive luminance and chromatic separation circuit - Google Patents

Abstract

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Description

Motion adaptive luminance and chromatic separation circuit

1 is a conventional brightness and chromaticity mixing circuit.

2 is an adaptive adaptive brightness and chromaticity separation circuit according to the present invention.

3 is a concrete diagram of the luminance / chromatic switching circuit of FIG.

4 is a characteristic diagram of an example of an approximation of an operation K constant according to the present invention.

5 is a detailed view of the motion coefficient K approximator according to the present invention.

6 is a detailed view of the product strength of the pipeline structure according to the present invention.

* Explanation of symbols for main parts of the drawings

11: A / D Converter 14: Motion Detector

15: Y / C separator 16, 17, 22, 23: adder

20, 21: Multiplier 18, 19 K coefficient approximator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a luminance and chromatic separation circuit for improving the image clarity of a high-definition TV. In particular, the multiplication constant for the luminance and chroma signal is adaptively changed according to the operation coefficient of the input video signal. A circuit for separating chroma signals.

In the current high-definition TV, the separation of luminance and chromaticity is performed to separate the luminance and chromaticity of the input video signal according to a correlation coefficient in the time axis direction in order to improve the clarity of the image quality.

1 is a conventional operation adaptive luminance and chromaticity separation circuit diagram, where a is a luminance switching circuit for separating luminance, and b is a chroma separation circuit for separating chromaticity.

Each switching circuit is composed of two multipliers M1, M2, M3, M4 and one adder SUM1, SUM2. In the figure, YL is a line luminance component, YF is a frame luminance component, CL is a line chroma component, CF is a frame chroma component, and YL and CL are line comb filters (not shown) and frame comb filters (not shown). Is the output.

1-K and K are operation coefficients output from a motion detector (not shown), 1-K is an operation coefficient of a video signal of a moving picture, and K is an operation coefficient of a still picture.

In the circuit of FIG. 1 as described above, the line luminance signal and chroma signals YL and CL output from the line comb filter are input to the multipliers M1 and M3, and the frame luminance signal and chroma signal YF output from the frame comb filter. When CF is input to the multipliers M2 and M4, the multipliers output a multiplication constant value by the input operation coefficients 1-K and K.

Therefore, the adder SUM1 adds the signals output from the multipliers M1 and M2 and outputs the luminance signal Ya = YF.K + (1-K) .YL which is operated. The adder SUM2 adds the signals output from the multipliers M3 and M4 to output the applied chroma signal Ca = CF.K + (1-K) .CL.

However, the conventional circuit as shown in FIG. 1 is complicated in the system by having two multipliers each for obtaining an operation-adapted luminance signal / chromatic signal. In addition, by using the output from the motion detector as it is, the number of parts of the hardware increases and the processing speed of the multiplication process is very slow, which has been a problem.

Accordingly, an object of the present invention is to provide a circuit for separately outputting luminance and chromaticity by adaptively changing a multiplication constant for luminance and chromaticity according to an operation coefficient of an input image signal.

Another object of the present invention is to provide a circuit that simplifies the multiplier in a pipeline structure and processes and outputs the luminance / chromatic signal of the input image signal into the adapted luminance / chromatic signal as one multiplier.

Another object of the present invention is to provide an operation coefficient approximator for approximating and outputting the operation coefficient K of the operation detector.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

2 is an adaptive adaptive luminance and chromaticity separation circuit diagram according to the present invention, which includes an A / D converter 11 for digitally converting and outputting an input image signal, and a line luminance and line separation by dividing the digitally converted image signal by line separation and frame separation. Y / C separator 15 for outputting chroma signal YL, CL, frame luminance signal and chroma signal YF, CF, and inputting the digital conversion video signal to detect the operation amount of the video signal and An operation detector 14 for outputting, an adder 16 and 17 for inputting and outputting the separated line luminance signal YL, the chroma signal CL, the frame luminance signal YF, and the chroma signal CF, respectively, and the motion detector 14; K coefficient approximators 18 and 19 for inputting an operation coefficient K of a predetermined bit outputted from the predetermined bit and approximating it to bits of a predetermined bit or less, and outputting the adder 16 and 17 and the K coefficient approximator. (18) (19) approximation coefficients KY, KC A multiplier (20) and a multiplier (20) and a multiplier and output the multiplier (18) and the output of the multiplier (18) and (19) and the line luminance signal (YL) and chroma signal (CL) of the Y / C separator (15). And adders 22 and 23 for outputting the signal Ya and the motion adaptive chromaticity signal Ca, respectively.

3 is a specific diagram of the luminance / chromatic switching circuit of FIG.

40 in FIG. 3 represents 16 or 17 of FIG. 2, 41 represents 18 or 19 of FIG. 2, 42 represents 20 or 21 of FIG. 2, and 43 represents 22 or 23 of FIG. 2.

40 denotes an adder, which latches the outputs of the delayers 24 and 25 and the delayers 20 and 25 for delaying the input signals YL / CL and YF / CF, respectively, by a predetermined clock, and outputs them synchronously at the same time. Latches 26 and 27, and an adder 28 to add the output of the latches 27 and 28.

41 is a K-factor approximator, the K-factor approximator 26 for approximating the operation coefficient K (K = 7 bits) of the latch 29 and the motion detector 14 to a 3-bit signal, and the K-factor approximation. The fire 26 is composed of a delay 31 and an output latch 32 for delaying the count value to be output at the same time as the output of the adder 28.

42 is a multiplier. The latch 33 and the multiplier 34 multiply and output the outputs of the delay unit 28 and the K coefficient approximator.

43 is an adder, which delays the output of the line luminance YL or the line chroma CL output from the latch 26 so that the multiplier 34 outputs the multiplication result and outputs the same at the same time; Two latches 36 and 37 and two latches 36 and 37 outputting the outputs of the delayer 35 and the multiplier 34 are synchronized to output an operation-adaptive luminance or chromaticity signal. An adder 38 and a latch 39 for latching and outputting the output of the adder 38.

All of the latches of FIG. 3 input a clock of 4fsc and synchronously output all signals.

FIG. 4 is a characteristic diagram of the K coefficient approximator of FIG. 2, which shows 9 levels by quantizing a transfer function characteristic when approximating an operation coefficient K of 7 bits to a value of 3 bits.

5 is a detailed diagram of the K coefficient approximator according to the present invention, and compares the operation amount detection operation coefficient K of the motion detector K with a predetermined threshold value, which is preset, and outputs a threshold determination bit value. The first, second, third, fourth, fifth, sixth, seventh, and eighth threshold detection circuits 64, 67, 70, 73, 76, 79, and 82 (85) and the threshold determination bit values of the first to eighth threshold detection circuits 64, 67, 70, 73, 76, 79, 82, and 85 It consists of a priority encoder 86 for encoding and outputting.

In this case, all the threshold detection circuits are an example in which two 4-bit comparators are configured in the present invention. In this case, FIG. 5 is hardware for satisfying the graph characteristics of FIG. 4, and the threshold value is only one example and can be changed according to the characteristics of the system.

에 의해 동기시켜 대치 출력하는 제3-제6래치(51-54)와, 상기 제3, 제4래치(51)(52)의 출력을 가산하여 제1가산결과를 출력하는 제1가산부(55)(56)와, 상기 제1가산부(55)(56)의 출력과 제5래치(53)의 연산결과 출력을 가산하여 그 가산결과를 출력하는 제2가산부(57)(58)와, 상기 제2가산부(57)(58)의 출력과 제6래치(54)의 연산결과의 출력을 가산하여 그 가산결과를 출력하는 제3가산부(59)(60)와, 상기 제3가산부(59)(60)의 출력을 래치 출력하는 래치(61)로 구성된다.6 is a detailed view of the multiplier of the pipeline structure according to the present invention, which is a detailed view of the multipliers 20 and 21 of FIG. The first latch 44 latches and outputs the 8-bit multiplier B1-B4 by the clock CLK, and the second latch latches and outputs the 4-bit multiplier A1-A4 by the clock CLK. 45), a register 50 for shifting out the upper three-bit output of the second latch 45 by the clock CLK input, a multiplicand of the first latch 44, and the second latch 45; First, second, third, and fourth operation units 46, 47, 48, and 49 for inputting a shift multiplication of the register 50 and outputting the result of the logical product; Clock the calculation result of the calculator 46-49

A first adder which adds outputs of the third and sixth latches 51-54 and the outputs of the third and fourth latches 51 and 52 to be synchronized with each other and outputs the first addition result. 55 and 56, and a second adder 57 and 58 for adding the output of the first adder 55 and 56 and the output of the calculation result of the fifth latch 53 and outputting the addition result. And third adders 59 and 60 for adding the outputs of the second adders 57 and 58 and the output of the calculation result of the sixth latch 54 and outputting the addition result. It consists of the latch 61 which latch-outputs the output of the 3 addition part 59 (60).

An operation example of FIG. 2 of the present invention will now be described with reference to FIGS. 3 to 6.

When the video signal is input to the A / D converter 11 of FIG. 2, it is digitally converted into the video signal and then input to the line, frame comb filter 12 (13) and the motion detector (14).

At this time, the line luminance signal YL / chromatic signal CL is output by the line comb filter 12, and the frame luminance signal YF / chromatic signal CF is output by the frame comb filter 13.

Here, the line comb filter 12 utilizes a characteristic in which moving images (moving pixels) have a small correlation coefficient with the time axis direction, but a correlation coefficient of a spatial region is increased. The line luminance signal YL / chromatic signal CL is extracted using a line memory. These are the signals of the same screen.

The frame luminance signal is an example in which the frame comb filter is configured as a frame memory by using a characteristic in which the YF and the chroma signal CF have high correlation coefficients in the time axis direction when they are still images.

The motion detector 14 is usually configured such that the coefficient of operation K approaches a value of 1 (K) in the case of a still picture, and approaches the value (1-K) of 0 in the case of a moving picture, and the output bit is 2 bits or more. The higher the bit, the finer the characteristic.

When the separate signal is output from the line comb filter 12 and the frame comb filter 13 as described above, and the motion detector 14 outputs the operation coefficient K of the video signal, the adder 16 generates the line luminance at the frame luminance signal YF. The operation value YF-YL is input to the multiplier 20 by subtracting the signal YL.

The adder 17 subtracts the line chroma signal CL from the frame chroma signal CF and inputs it to the (CF-CL) multiplier 21.

Therefore, the output of the adder 16 and the K coefficient are multiplied by the output 4-bit (approximate value) coefficient KY multiplier 20 of the approximator 18, thereby calculating the value of (YF-YL).

The output of the multiplier 20 is added to the line luminance signal YL by the adder 22 and output as an operation adaptive luminance signal of (YF-YL) and KY + YL. If the output of the adder 22 is rearranged, it can be seen that Equation (1) is the same as that of FIG.

(YF-YL) KY + YL = YF ・ KY + (1-KY) YL ..................... (1)

On the other hand, the multiplier 21 outputs the value of (CF-CL) Ke by inputting the output CF-CL of the adder 17 and the approximation coefficient KC of the K coefficient approximator 19, which is an adder 23. ) Is added to the line chroma signal CL and output as an operation adaptive chromatic signal CF-CL, KC + CL = CF, Ke + (1-KC) CL.

Therefore, in case of a still picture, the K coefficient approaches 1, so the output of the frame comb filter 13 is mainly selected. In the case of moving pictures, the K coefficient approaches 0, so the output of the line comb filter 12 is mainly selected. In this case, the output of the frame and line comb filters 13 and 12 is adaptively synthesized according to the K coefficient, thereby obtaining a perfect three-dimensional signal characteristic.

The operation of the K-factor approximator 18 or 19 in FIG. 2 is described as follows.

When the coefficient value K (4,10,18,28,40,56,74,94; decimal notation) is output from the motion detector 14 as a 7-bit signal like the horizontal axis of FIG. The first to eighth threshold detection circuits 64, 67, 70, 73, 76, 79, 82 and 85 are input to the comparators.

At this time, the threshold values of all the threshold detectors are set to values of the vertical axis of FIG. 4 as shown in the following table.

TABLE 1

Therefore, when the input operation coefficient K is larger than 4, the terminal A> B of the comparator 63 is output to the logic # 1 ', and the signal of # 0000 0001 "is input to the encoder 86 first.

If the input operation coefficient K is larger than 94, the output terminals A > B of the comparators 63, 66, 69, 72, 75, 78, 81, and 84 are all ＂1＂. The encoder 86 inputs a signal of 1111 1111.

At this time, the priority encoder 86 decodes and outputs a priority signal to be input into a 3-bit signal, and the multiplier 18 and 19 described above include a 4-bit approximated operation coefficient KC / including the most significant bit grounded. It is input as a signal of KY. In the above, the threshold value is only one example, and can be changed according to system characteristics.

On the other hand, the output of the adder 16 in Fig. 2 (YF-YL) and the multiplier 20 to perform the multiplication operation by inputting the approximate operation coefficient KX (KY) of Fig. 5 and the output of the adder 17 And (CF-CL) and the approximate operation coefficient KK (KC) of FIG. 5, and the multiplication operation is performed with reference to FIG. 6 of FIG.

6 is a detailed structural diagram of the multipliers 20 and 21. An 8-bit multiplier is input to the first latch 44 by the patch clock CLK, and the second latch 45 is set to 4 by the latch clock CLK. Bit multiplier is input.

The 8-bit multiplier is the output of the adder 16 or 17 and the multiplier is the 4-bit output of the K-factor approximator 18 or 19.

FIG. 6 of the present invention is designed to obtain a multiplication result of the following third equation.

TABLE 2

In this case, C denotes CARRY, ignoring the □ mark and indicates that it is not used. The maximum 12 bytes can be used if necessary, but only the upper 8 bits are used here.

As described above, when an 8-bit multiplier and a 4-bit beast are input to the first and second latches 44 and 45, the multiplicands B1-B8 of the first latch 44 are each formed of eight end gates. Inputs are made to the first-fourth calculation units 46, 47, 48, and 49, respectively. At this time, only the least significant bit A1 of the four bits latched by the second latch 45 is input to the first operation unit 46, and other signals A2-A4 are input to the latch-in registers 16 and 17.

Therefore, the calculation result of B8A1, B7A1, B6A1, B5A1, B4A1, B3A1, B2A1, B1A1 is output from the 1st operation part 46, and is input to the 3rd latch 51.

When the clock CLK is input in the above state, the clock CLK is delayed by one clock in the A2 register 50 of the second latch 45 and input to the second operation unit 47. Therefore, the second calculation unit 47 outputs the same calculation result as B8A2, B7A2, B6A2, B5A2, B4A2, B3A2, B2A2, B2A1, and the second multiplication result is output to the fourth latch 52. Is entered.

In addition, A3 and A4 of the second latch 45 are delayed by 2 and 3 clocks by the adder register 50, respectively, and are respectively input to the third and fourth calculation units 48 and 49, thereby providing the calculation units 48 and 49. ) Outputs as shown in (c) (d) of the third expression.

The result of the multiplication obtained as described above is that the timing is synchronized by the third to sixth latches 51-54, and then the first to third adders 55, 56, 57, 58, 59 and 60 are made. Are added to each other, and addition is performed.

At this time, the least significant bit of the third latch 51 is undone and B1A1 is ignored, and the output terminals of the adders 55, 57 and 59 are all undone so that the least significant bit corresponding to the addition is S1, S1 ', S1'. Are ignored, and the carry output of the adder 60 is input to the most significant bit terminal of the latch 61.

Therefore, the result multiplied by the first-fourth operation units 46-49 is added by the first-third addition units 55, 56, 57, 58, 59, and 60 as shown in the third equation. Only the multiplication result signal of the necessary upper 8 bits is performed and input to the above-described adder 22 or 23 via the latch 61.

As described above, the present invention can reduce the multiplier by performing the multiplication operation as a multiplier of the pipeline structure in implementing the operation-adaptive luminance / chromatic circuit, and maintains the characteristics of the operation coefficient of a predetermined bit output from the motion detector. It is easy to integrate by simplifying the circuit by approximating the coefficient K.

Claims (3)

An A / D converter 11 for digitally converting and outputting an input video signal, and outputting line luminance and chroma signals YL, CL, frame luminance signals, and chroma signal YF, CF by separating the digitally converted video signals by line separation and frame separation. An operation adaptive luminance and chromaticity separation circuit having a Y / C separator 15, comprising: an operation detector for inputting the digital conversion video signal to detect an operation amount of the video signal and outputting an operation coefficient K of a predetermined bit; 14), adders 16 and 17 for inputting and outputting the separated line luminance signal YL, the chroma signal CL, the frame luminance signal YF, and the chroma signal CF, respectively, and a predetermined output from the operation detector 14; K coefficient approximators 18 and 19 for inputting an operation coefficient K of a bit and approximating it to bits of a predetermined bit or less, and outputting the adders 16 and 17 and the K coefficient approximator 18 and 19 Input the approximate coefficients KY, KC Multiply outputs the multipliers 20 and 21, the outputs of the multipliers 18 and 19, the line luminance signal YL and the chroma signal CL of the Y / C separator 15, respectively, and inputs the operation adaptive luminance signal Ya and And an adder (22) (23) for respectively outputting the operating adaptive chromaticity signal Ca. 2. The threshold determination bit according to claim 1, wherein each of the K coefficient approximators 18 and 19 compares the operation amount detection operation coefficient K of the motion detector K with a preset unique threshold value. First, second, third, fourth, fifth, sixth, seventh, and eighth threshold detection circuits 64, 67, 70, 73, 76, 79 that output a value. (82) 85 and the threshold determination bit values of the first to eighth threshold detection circuits 64, 67, 70, 73, 76, 79, 82, and 85 Circuit comprising a Priority Encoder (86) for encoding and outputting the encoded signal. The first latch 44 which latches 8 multiplicands B1-B4 by the clock CLK to the multipliers 20 and 21, and a multiplier A1-A4. Latch 45 for latching and outputting the clock by the clock CLK, the register 50 for shifting out the upper 3 bits output of the second latch 45 by the clock CLK input, and the first latch ( First, second, third, and fourth operation units 46 and 47 which input a multiplier of 44 and a shift multiplier of the second latch 45 and the register 50 to output the result of the logical product. 48) 49 and the operation results of the first-fourth operation units 46-49 are clocked.

1st adder which adds the 3rd-6th latch 51-54 which substitutes and outputs the synchronously and the output of the said 3rd, 4th latch 51, 52, and outputs a 1st addition result ( 55 and 56, and a second adder 57 and 58 for adding the output of the first adder 55 and 56 and the output of the calculation result of the fifth latch 53 and outputting the addition result. And third adders 59 and 60 for outputting the second adders 57 and 58 and the output of the calculation result of the sixth latch 54 and outputting the addition result. And a latch (61) for latching and outputting the outputs of the adder (59) (60).

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