[go: up one dir, main page]

KR920001692A - Zero Power IC Module - Google Patents

Zero Power IC Module Download PDF

Info

Publication number
KR920001692A
KR920001692A KR1019910009440A KR910009440A KR920001692A KR 920001692 A KR920001692 A KR 920001692A KR 1019910009440 A KR1019910009440 A KR 1019910009440A KR 910009440 A KR910009440 A KR 910009440A KR 920001692 A KR920001692 A KR 920001692A
Authority
KR
South Korea
Prior art keywords
battery
power
finger
lead
offset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
KR1019910009440A
Other languages
Korean (ko)
Other versions
KR100206533B1 (en
Inventor
큐작 다니엘
킹스톤 로빈슨 리챠드
세리 후세 키미
Original Assignee
리챠드 케이. 로빈슨
에스지에스-톰슨 마이크로일렉트로닉스, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 리챠드 케이. 로빈슨, 에스지에스-톰슨 마이크로일렉트로닉스, 인코포레이티드 filed Critical 리챠드 케이. 로빈슨
Publication of KR920001692A publication Critical patent/KR920001692A/en
Application granted granted Critical
Publication of KR100206533B1 publication Critical patent/KR100206533B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49593—Battery in combination with a leadframe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01055—Cesium [Cs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
    • H05K2203/304—Protecting a component during manufacturing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Battery Mounting, Suspending (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

내용 없음No content

Description

제로 전력 IC 모듈Zero Power IC Module

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 제1실시예의 따라 백업 배터리의 음극 단자상에 집적회로 칩이 장착되어 있는 리이드 프레임 조립체의 평면도.1 is a plan view of a lead frame assembly in which an integrated circuit chip is mounted on a negative terminal of a backup battery according to a first embodiment of the present invention.

제2도는 단일 모울딩 패키지 내의 반도체 집적회로와 라이드 프레임의 부분 파단 측면도.2 is a partially broken side view of a semiconductor integrated circuit and a ride frame in a single molding package.

제3도는 제2도의 집적회로, 백업 배터리 및 핑거 리이드 조립체의 부분 파단평면도.3 is a partially broken plan view of the integrated circuit, backup battery and finger lead assembly of FIG.

Claims (11)

전자회로 소자에 전력을 공급하는 소자 패키지에 있어서; 비-전도성 재료의 본체와; 상기 비-전도성 재료의 본체내에 캡슐화되고, 핑거 리이드들중 하나는 전력 리이드를형성하는 다수의 전도성 핑거 리이드들을 포함하는 핑거 리이드 조립체와; 양극 전력 단자와 음극 전력 단자를 가지며, 상기 단자들중의 하나는 상기 전력 리이드상에 설치되는 배터리와; 상기 비-전도성 재료의 본체내에 캡슐화되고 상기 다른 배터리 전력 단자상에서 장착되는 전자회로 소자들로 구성되며; 상기 전력 리이드는 상기 전력 리이드 조립체에 대하여 어긋난 관계로 오프셋 되어 있으며, 상기 배터리는 상기 오프셋 전력 라이드상에 장착됨을 특징으로 하는 소자 패키지.A device package for supplying power to an electronic circuit device; A body of non-conductive material; A finger lead assembly encapsulated within the body of the non-conductive material, one of the finger leads including a plurality of conductive finger leads forming a power lead; A battery having a positive power terminal and a negative power terminal, one of the terminals provided on the power lead; Consists of electronic circuit elements encapsulated in a body of said non-conductive material and mounted on said other battery power terminal; The power lead is offset in a misaligned relationship with respect to the power lead assembly, and the battery is mounted on the offset power ride. 제1항에 있어서, 상기 전도성 리이드는 기다란 간격으로 분리되는 제1, 제2연결 바아 부분들로 구성되고 상기 배터리는 상기 연결 바아 부분들중 적어도 하나에 장착됨을 특징으로 하는 소자 패키지.The device package of claim 1, wherein the conductive lead is composed of first and second connection bar portions separated at long intervals and the battery is mounted to at least one of the connection bar portions. 제1항에 있어서, 상기 전도성 핑거 리이드들은 상호 접속 영역 주변에 이격되어 있고, 상기 전력 리이드는 상기 상호 접속 영역을 가로지르는 오프셋 베이스판 지지부를 포함하며, 상기 배터리 단자들중의 하나는 상기 베이스판 지지부상에 설치되어 전기적으로 연결됨을 특징으로 하는 소자 패키지.10. The substrate of claim 1, wherein the conductive finger leads are spaced around an interconnect area, the power lead including an offset base plate support across the interconnect area, wherein one of the battery terminals is the base plate. A device package, characterized in that installed on the support and electrically connected. 제1항에 있어서, 상기 전자회로 소자는 반도체 칩상에서 수행되는 집적회로이고; 상기 칩은 상기 다른 배터리 단자에 스태크된 관계로 기계적으로 잗착되어 전기적으로 연결되며; 상기 집적회는 다수의 입력/출력 노드들과 상기 입력/출력 노드들을 상기 전도성 핑거 리이드들에 연결하는 다수의 와이어 도체들과, 상기 칩이 장착된 배터리 단자와 상기 오프셋베이스 지지부 각각에 상기 와이어 도체들에 의해 전기적으로 연결되는 양극 및 음극 전력 노드들을 갖는 것을 특징으로 하는 소자 패키지.The semiconductor device according to claim 1, wherein the electronic circuit element is an integrated circuit performed on a semiconductor chip; The chip is mechanically attached and electrically connected in a stacked relationship to the other battery terminal; The integrated circuit comprises a plurality of input / output nodes and a plurality of wire conductors connecting the input / output nodes to the conductive finger leads, a battery terminal on which the chip is mounted, and the wire conductor on each of the offset base supports. Device comprising a positive and negative power nodes electrically connected by the respective devices. 제1항에 있어서, 상기 배터리에는 양극 및 음극 접촉 단자들이 있고, 상기 음극 접촉 단자는 상기 오프셋 전력 리이드에 장착되어 전기적으로 연결됨을 특징으로 하는 소자 패키지.The device package of claim 1, wherein the battery has positive and negative contact terminals, and the negative contact terminal is mounted to and electrically connected to the offset power lead. 제1항에 있어서, 상기 배터리에는 양극 및 음극 접촉 단자들이 있고, 상기 양극 접촉 단자는 상기 오프셋 전력 리이드에 장착되어 전기적으로 연결됨을 특징으로 하는 소자 패키지.The device package of claim 1, wherein the battery has positive and negative contact terminals, and the positive contact terminal is mounted on the offset power lead and electrically connected thereto. 제1항에 있어서, 상기 소자 패키지는 상기 칩과 상기 다른 배터리 전력 단자 사이에 삽입된 비-전도성 결합기판을 포함함을 특징으로 하는 소자 패키지.2. The device package of claim 1, wherein the device package comprises a non-conductive coupled substrate inserted between the chip and the other battery power terminal. 제7항에 있어서, 상기 결합 기판에는 연결 구멍이 뚫려있고; 상기 전자회로 소자는 반도체 칩상에서 수행되는 집적회로이며; 상기 칩은 스테크된 관계로 상기 결합 기판상에 장착되고; 상기 집적회로 소자는 다수의 입력/출력 노드들과 상기 입력/출력 노드들을 상기 전도성 핑거 리이드들에 연결하는 다수의 와이어 도체들과, 상기 결합 기판이 장착되는 배터리 단자와 상기 오프셋 전력 리이드에 각각 상기 와이어 도체들에 의해 전기적으로 연결되는 양극 및 음극 전력 노드들을 갖으며; 상기 와이어 도체들중 하나는 상기 집적회로 소자로부터 상기 연결 구멍을 통해 상기 결합기판이 장착된 배터리 단자까지 연장됨을 특징으로 하는 소자 패키지.The method of claim 7, wherein the bonding substrate is bored with a connection hole; The electronic circuit element is an integrated circuit performed on a semiconductor chip; The chip is mounted on the bonding substrate in a stacked relationship; The integrated circuit device may include a plurality of input / output nodes and a plurality of wire conductors connecting the input / output nodes to the conductive finger leads, a battery terminal on which the coupling substrate is mounted, and the offset power lead, respectively. Having positive and negative power nodes electrically connected by wire conductors; One of the wire conductors extends from the integrated circuit element through the connection hole to a battery terminal on which the coupling substrate is mounted. 제1항에 있어서, 상기 배터리는 기밀 봉지됨을 특징으로 하는 소자 패키지.The device package of claim 1, wherein the battery is hermetically sealed. 비-전도성 재료의 본체내에 캡슐화된 다수의 입력/출력 노드들과 상기 비-전도성 재료의 본체위에 장착되어 본체 외부로 돌출하는 다수의 커넥터 리이드들과, 상기 비-전도성 재료의 본체내에 캡슐화되어 상기 입력/출력 노드들을 상기 커넥터 리이드들에 전기적으로 연결하는 다수의 전도성 핑거 리이드로 이루어지는 핑거 리이드 조립체를 포함하는 회로 소자를 갖는 형태의 전자회로 패키지에 있어서; 다수의 상기 전도성 핑거 리이드들에는 상기 상호 접속 영역에 대하여 이격되어 있는 내단부들이 있고; 상기 전도성 핑거 리이드들중의 하나는 전력 리이드를 이루고 상기 상호 접속영역을 가로지르는 베이스 지지부를 가지며, 상기 베이스 지지부는 상기 핑거리이드 조립체 평면에 어긋난 관계로 오프셋되어 있고; 배터리에는 양극 및 음극 단자들이 있으며, 상기 전력 단자들중의 하나는 상기 전력 리이드의 베이스 지지부에 장착되어 전기적으로 연결되며, 상기 회로 소자는 다른 배터리 전력 단자에 장착됨을 특징으로 하는 전자회로 패키지.A plurality of input / output nodes encapsulated within the body of non-conductive material and a plurality of connector leads mounted on the body of the non-conductive material and projecting out of the body, encapsulated within the body of the non-conductive material An electronic circuit package having a circuit element comprising a finger lead assembly comprising a plurality of conductive finger leads electrically connecting input / output nodes to the connector leads; A plurality of the conductive finger leads have inner ends spaced apart from the interconnect area; One of the conductive finger leads has a base support that constitutes a power lead and crosses the interconnect area, the base support being offset in an offset relationship with the finger lead assembly plane; The battery has positive and negative terminals, one of the power terminals mounted on and electrically connected to the base support of the power lead, and the circuit element mounted to the other battery power terminal. 전자회로 소자에 전력을 공급하는 배터리와 전자 회로 소자를 패키지하는 방법에 있어서: 동일 평면상의 핑거 리이드 조립체의 핑거 리이드들을 상호 접속 영역에 대하여 이격되게 배열하는 단계와; 상기 핑거 리이드 조립체 평면에 어긋난 오프셋된 관계로 상기 상호 접속 영역내에 전력 핑거 리이드를 지지하는 단계와; 상기 오프셋 전력 핑거 리이드에 배터리의 전력 단자를 장착하는 단계와; 상기 배터리의 다른 전력 단자에 상기 전자회로를 설치하는 단계와; 상기 전자회로 소자, 배터리 전력 리이드 및 핑거 리이드 조립체의 상기 스테크된 조립체를 비-전도성 재료의 본체내에 캡슐화하는 단계들로 구성됨을 특징으로 하는 패키지 방법.A method of packaging a battery and an electronic circuit element for powering an electronic circuit element, the method comprising: arranging finger leads of a coplanar finger lead assembly spaced apart from an interconnection area; Supporting a power finger lead in the interconnect area in an offset relationship against the finger lead assembly plane; Mounting a power terminal of a battery to said offset power finger lead; Installing the electronic circuit at the other power terminal of the battery; Encapsulating said stacked assembly of said electronics element, battery power lead and finger lead assembly in a body of non-conductive material. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910009440A 1990-06-06 1991-06-05 Zero Power IC Module Expired - Fee Related KR100206533B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US07/534.151 1990-06-06
US7/534.151 1990-06-06
US07/534,151 US5089877A (en) 1990-06-06 1990-06-06 Zero power ic module

Publications (2)

Publication Number Publication Date
KR920001692A true KR920001692A (en) 1992-01-30
KR100206533B1 KR100206533B1 (en) 1999-07-01

Family

ID=24128888

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910009440A Expired - Fee Related KR100206533B1 (en) 1990-06-06 1991-06-05 Zero Power IC Module

Country Status (4)

Country Link
US (1) US5089877A (en)
EP (1) EP0460801A3 (en)
JP (1) JPH0738028A (en)
KR (1) KR100206533B1 (en)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5008776A (en) * 1990-06-06 1991-04-16 Sgs-Thomson Microelectronics, Inc. Zero power IC module
US5323150A (en) * 1992-06-11 1994-06-21 Micron Technology, Inc. Method for reducing conductive and convective heat loss from the battery in an RFID tag or other battery-powered devices
US5371654A (en) * 1992-10-19 1994-12-06 International Business Machines Corporation Three dimensional high performance interconnection package
US20050062492A1 (en) * 2001-08-03 2005-03-24 Beaman Brian Samuel High density integrated circuit apparatus, test probe and methods of use thereof
TW270213B (en) * 1993-12-08 1996-02-11 Matsushita Electric Ind Co Ltd
US6416714B1 (en) 1995-04-25 2002-07-09 Discovery Partners International, Inc. Remotely programmable matrices with memories
US6017496A (en) 1995-06-07 2000-01-25 Irori Matrices with memories and uses thereof
US5874214A (en) 1995-04-25 1999-02-23 Irori Remotely programmable matrices with memories
US6331273B1 (en) 1995-04-25 2001-12-18 Discovery Partners International Remotely programmable matrices with memories
US5751629A (en) * 1995-04-25 1998-05-12 Irori Remotely programmable matrices with memories
US6329139B1 (en) 1995-04-25 2001-12-11 Discovery Partners International Automated sorting system for matrices with memory
EP0895287A3 (en) * 1997-07-31 2006-04-05 Matsushita Electric Industrial Co., Ltd. Semiconductor device and lead frame for the same
US6075742A (en) * 1997-12-31 2000-06-13 Stmicroelectronics, Inc. Integrated circuit for switching from power supply to battery, integrated latch lock, and associated method for same
US6109530A (en) * 1998-07-08 2000-08-29 Motorola, Inc. Integrated circuit carrier package with battery coin cell
DE19927285C2 (en) * 1999-06-15 2003-05-22 Eupec Gmbh & Co Kg Low-inductance semiconductor component
US7034402B1 (en) * 2000-06-28 2006-04-25 Intel Corporation Device with segmented ball limiting metallurgy
US7230321B2 (en) * 2003-10-13 2007-06-12 Mccain Joseph Integrated circuit package with laminated power cell having coplanar electrode
US7557433B2 (en) 2004-10-25 2009-07-07 Mccain Joseph H Microelectronic device with integrated energy source
US7180171B1 (en) 2004-01-08 2007-02-20 Smart Modular Technologies, Inc. Single IC packaging solution for multi chip modules
JP2011140365A (en) * 2010-01-05 2011-07-21 Asahi Organic Chemicals Industry Co Ltd Conveying roller and belt conveyor using the same
TW202236570A (en) * 2021-03-12 2022-09-16 華東科技股份有限公司 System in package characterized in that the system in package can achieve the effects of greatly thinning the thickness of the package and lowering the whole cost by not having the printed circuit board in the package structure
TWI791200B (en) * 2021-03-12 2023-02-01 華東科技股份有限公司 Thin System-in-Package
US20250174531A1 (en) * 2023-11-28 2025-05-29 Nxp Usa, Inc. Electronic package with a battery secured by a bent leadframe

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4142287A (en) * 1976-12-27 1979-03-06 Amp Incorporated Electrical devices such as watches and method of construction thereof
JPS57109183A (en) * 1980-12-26 1982-07-07 Hitachi Ltd Non-volatile memory
US4616655A (en) * 1984-01-20 1986-10-14 Cordis Corporation Implantable pulse generator having a single printed circuit board and a chip carrier
JPS61108160A (en) * 1984-11-01 1986-05-26 Nec Corp Semiconductor device with built-in capacitor and manufacture thereof
US5008776A (en) * 1990-06-06 1991-04-16 Sgs-Thomson Microelectronics, Inc. Zero power IC module

Also Published As

Publication number Publication date
US5089877A (en) 1992-02-18
JPH0738028A (en) 1995-02-07
EP0460801A3 (en) 1993-03-03
KR100206533B1 (en) 1999-07-01
EP0460801A2 (en) 1991-12-11

Similar Documents

Publication Publication Date Title
KR920001692A (en) Zero Power IC Module
KR920001691A (en) Zero Power IC Module
US6891257B2 (en) Packaging system for die-up connection of a die-down oriented integrated circuit
CA1201820A (en) Semiconductor integrated circuit including a lead frame chip support
US4975763A (en) Edge-mounted, surface-mount package for semiconductor integrated circuit devices
US6774465B2 (en) Semiconductor power package module
EP0001892B1 (en) Lead frame and package for establishing electrical connections to electronic components
KR101062260B1 (en) Integrated circuit assembly
US5260601A (en) Edge-mounted, surface-mount package for semiconductor integrated circuit devices
US6610923B1 (en) Multi-chip module utilizing leadframe
KR970067801A (en) Semiconductor device and manufacturing method thereof
KR920001696A (en) Heat sink and multiple mounting pad lead frame package and method for isolating semiconductor die
KR950001971A (en) Test Sockets for Known Good Die Arrays
KR950030323A (en) Semiconductor device and production method of semiconductor device and semiconductor module
GB1488759A (en) Electrical assemblies
US5504370A (en) Electronic system circuit package directly supporting components on isolated subsegments
KR980006184A (en) Semiconductor integrated circuit device
KR870009613A (en) Integrated Circuit Chip Mounting & Packaging Assemblies
KR890013751A (en) Semiconductor devices
US4885662A (en) Circuit module connection system
EP0721209A3 (en) Method of testing semiconductor devices and conductive adhesive thereby used
JPH1126678A (en) Lead structure for electronic part
TW550713B (en) Package for electronic components and method for forming a package for electronic components
KR920010845A (en) Integrated Circuit Package with Mold Cells
KR970002136B1 (en) Semiconductor package

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

FPAY Annual fee payment

Payment date: 20020403

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20030409

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20030409

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000