[go: up one dir, main page]

KR910017382U - Multibit parallel test circuit - Google Patents

Multibit parallel test circuit

Info

Publication number
KR910017382U
KR910017382U KR2019900002769U KR900002769U KR910017382U KR 910017382 U KR910017382 U KR 910017382U KR 2019900002769 U KR2019900002769 U KR 2019900002769U KR 900002769 U KR900002769 U KR 900002769U KR 910017382 U KR910017382 U KR 910017382U
Authority
KR
South Korea
Prior art keywords
test circuit
parallel test
multibit parallel
multibit
circuit
Prior art date
Application number
KR2019900002769U
Other languages
Korean (ko)
Other versions
KR960007140Y1 (en
Inventor
정원화
Original Assignee
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성일렉트론 주식회사 filed Critical 금성일렉트론 주식회사
Priority to KR2019900002769U priority Critical patent/KR960007140Y1/en
Publication of KR910017382U publication Critical patent/KR910017382U/en
Application granted granted Critical
Publication of KR960007140Y1 publication Critical patent/KR960007140Y1/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30Accessing single arrays
    • G11C29/34Accessing multiple bits simultaneously
KR2019900002769U 1990-03-09 1990-03-09 Multibit parallel test circuit KR960007140Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019900002769U KR960007140Y1 (en) 1990-03-09 1990-03-09 Multibit parallel test circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019900002769U KR960007140Y1 (en) 1990-03-09 1990-03-09 Multibit parallel test circuit

Publications (2)

Publication Number Publication Date
KR910017382U true KR910017382U (en) 1991-10-28
KR960007140Y1 KR960007140Y1 (en) 1996-08-22

Family

ID=19296622

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019900002769U KR960007140Y1 (en) 1990-03-09 1990-03-09 Multibit parallel test circuit

Country Status (1)

Country Link
KR (1) KR960007140Y1 (en)

Also Published As

Publication number Publication date
KR960007140Y1 (en) 1996-08-22

Similar Documents

Publication Publication Date Title
DE69127196D1 (en) ANTIOXIDANT TEST
DE68921269D1 (en) Integrated test circuit.
DE68926589D1 (en) Tester
DE69131531D1 (en) Integrating circuit
DE69119152D1 (en) Circuit arrangement
DE69031729D1 (en) MODULATOR CIRCUIT
DE69025110D1 (en) Test device
DE69130755D1 (en) Test facility
DE69026551D1 (en) Integrator circuit
ATA247090A (en) TERMINAL ARRANGEMENT
FI952318L (en) Telechannel testing arrangement
DE69029634D1 (en) Test latch circuit
ATA258289A (en) DRYING DEVICE
DE69029468D1 (en) Integrated circuit arrangement
DE69127149D1 (en) Circuit test procedure
ATA258189A (en) DRYING DEVICE
DE68928600D1 (en) Extended test circuit
DE69024711D1 (en) Amplifier circuit
DE69024865D1 (en) Amplifier circuit
DE69117097D1 (en) Test fixtures
KR910017382U (en) Multibit parallel test circuit
KR910013424U (en) Sensitivity improvement circuit
KR920010235U (en) ROM test circuit
FR2648943B1 (en) SAMPLE-LOCKER CIRCUIT
DE59010443D1 (en) Integrated circuit arrangement

Legal Events

Date Code Title Description
UA0108 Application for utility model registration

Comment text: Application for Utility Model Registration

Patent event code: UA01011R08D

Patent event date: 19900309

UG1501 Laying open of application
A201 Request for examination
UA0201 Request for examination

Patent event date: 19930309

Patent event code: UA02012R01D

Comment text: Request for Examination of Application

Patent event date: 19900309

Patent event code: UA02011R01I

Comment text: Application for Utility Model Registration

UG1604 Publication of application

Patent event code: UG16041S01I

Comment text: Decision on Publication of Application

Patent event date: 19960729

E701 Decision to grant or registration of patent right
UE0701 Decision of registration

Patent event date: 19961112

Comment text: Decision to Grant Registration

Patent event code: UE07011S01D

REGI Registration of establishment
UR0701 Registration of establishment

Patent event date: 19961206

Patent event code: UR07011E01D

Comment text: Registration of Establishment

UR1002 Payment of registration fee

Start annual number: 1

End annual number: 3

Payment date: 19961205

UR1001 Payment of annual fee

Payment date: 19990729

Start annual number: 4

End annual number: 4

UR1001 Payment of annual fee

Payment date: 20000724

Start annual number: 5

End annual number: 5

UR1001 Payment of annual fee

Payment date: 20010725

Start annual number: 6

End annual number: 6

UR1001 Payment of annual fee

Payment date: 20020716

Start annual number: 7

End annual number: 7

UR1001 Payment of annual fee

Payment date: 20030718

Start annual number: 8

End annual number: 8

FPAY Annual fee payment

Payment date: 20040719

Year of fee payment: 9

UR1001 Payment of annual fee

Payment date: 20040719

Start annual number: 9

End annual number: 9

LAPS Lapse due to unpaid annual fee
UC1903 Unpaid annual fee