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KR910013684A - GM SK Digital Modulation Circuit - Google Patents

GM SK Digital Modulation Circuit Download PDF

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Publication number
KR910013684A
KR910013684A KR1019890019929A KR890019929A KR910013684A KR 910013684 A KR910013684 A KR 910013684A KR 1019890019929 A KR1019890019929 A KR 1019890019929A KR 890019929 A KR890019929 A KR 890019929A KR 910013684 A KR910013684 A KR 910013684A
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KR
South Korea
Prior art keywords
signal
memory means
mapping
analog
circuit
Prior art date
Application number
KR1019890019929A
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Korean (ko)
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KR950005149B1 (en
Inventor
박상규
Original Assignee
정용문
삼성전자 주식회사
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Priority to KR1019890019929A priority Critical patent/KR950005149B1/en
Publication of KR910013684A publication Critical patent/KR910013684A/en
Application granted granted Critical
Publication of KR950005149B1 publication Critical patent/KR950005149B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20—Modulator circuits; Transmitter circuits
    • H04L27/2003—Modulator circuits; Transmitter circuits for continuous phase modulation
    • H04L27/2007—Modulator circuits; Transmitter circuits for continuous phase modulation in which the phase change within each symbol period is constrained
    • H04L27/2017—Modulator circuits; Transmitter circuits for continuous phase modulation in which the phase change within each symbol period is constrained in which the phase changes are non-linear, e.g. generalized and Gaussian minimum shift keying, tamed frequency modulation

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

내용 없음.No content.

Description

지엠에스케이 디지탈 변조회로GM SK Digital Modulation Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 GMSK 변조기의 기능별 블럭다이어그램,2 is a functional block diagram of a GMSK modulator,

제3도는 본 발명에 따른 GMSK 변조기 블럭도,3 is a GMSK modulator block diagram according to the present invention;

제4도는 가우시안 필터의 단일 구형파 응답도.4 is a single square wave response of a Gaussian filter.

Claims (4)

지엠에스케이 변조신호 발생회로에 있어서, 가우시안 필터의 출력에 의한 위상 변화량의 여현 및 정현함수값을 각각 저장하는 메모리수단과, 상기 메모리수단의 어드레스를 지정하는 어드레스 지정수단과, 상기 메모리수단으로부터 돌출된 데이타를 아날로그화 하는 아날로그 처리수단과, 상기 아날로그 데이타를 각각 캐리어 신호 혹은 소정 위상천이된 캐리어 신호와 혼합하고 그 결과를 합성하여 GMSK 변조신호를 발생하는 사상변조 수단으로 구성됨을 특징으로 하는 회로.In the GM-SC modulation signal generating circuit, memory means for storing the cosine and sine function values of the phase change amount by the output of the Gaussian filter, addressing means for designating an address of the memory means, and protruding from the memory means. And analog mapping means for analogizing data, and mapping modulating means for mixing the analog data with a carrier signal or a carrier signal having a predetermined phase shift, and synthesizing the result to generate a GMSK modulated signal. 제1항에 있어서, 어드레스 지정수단이 소정 주파수의 클럭신호를 소정 분주하는 분주기와, 디지탈신호를 입력하여 상기 분주기 출력상태에 따라 상기 메모리 수단으로 여현 및 정현함수 데이타 독출을 위한 어드레스 신호를 발생하는 쉬프트레지스터와, 위상 변화의 초기 값과 계속되는 누적 값을 결정하는 위상제어기와, 상기 클럭신호를 소정수 카운트하여 한비트 구간내에서 상기 메모리 수단으로 부터 상기 카운트값 만큼의 값을 독출할 수 있도록 제어하는 카운터로 구성됨을 특징으로 하는 회로.2. The apparatus of claim 1, wherein the addressing means divides a clock signal of a predetermined frequency into a predetermined frequency, and inputs a digital signal to provide an address signal for reading cosine and sine function data to the memory means in accordance with the output state of the frequency divider. A shift register to be generated, a phase controller for determining an initial value of a phase change and a continuous cumulative value, and a predetermined number of counts of the clock signal to read out the count value from the memory means within one bit period. A circuit comprising a counter for controlling so that. 제1항에 있어서, 상기 아날로그 처리수단과 상기 사상변조수단 사이에 저역필터수단을 더 구비하여 아날로그 함수값의 양자화 잡음을 제거하도록 구성함을 특징으로 하는 회로.2. The circuit according to claim 1, further comprising a low pass filter means between the analog processing means and the mapping modulator to remove quantization noise of an analog function value. 제1항에 있어서, 상기 사상변조기 출력단에 대역통과필터를 더 구비하여 지엠에스케이 변조신호의 고주파성분을 제거함을 특징으로 하는 회로.2. The circuit of claim 1, further comprising a band pass filter at the output of the mapping modulator to remove high frequency components of the GM-es modulated signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890019929A 1989-12-28 1989-12-28 GM SK Digital Modulation Circuit KR950005149B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890019929A KR950005149B1 (en) 1989-12-28 1989-12-28 GM SK Digital Modulation Circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890019929A KR950005149B1 (en) 1989-12-28 1989-12-28 GM SK Digital Modulation Circuit

Publications (2)

Publication Number Publication Date
KR910013684A true KR910013684A (en) 1991-08-08
KR950005149B1 KR950005149B1 (en) 1995-05-18

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ID=19293993

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890019929A KR950005149B1 (en) 1989-12-28 1989-12-28 GM SK Digital Modulation Circuit

Country Status (1)

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KR (1) KR950005149B1 (en)

Also Published As

Publication number Publication date
KR950005149B1 (en) 1995-05-18

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