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KR910012958A - How Interrupt Buses Are Synchronized - Google Patents

How Interrupt Buses Are Synchronized Download PDF

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Publication number
KR910012958A
KR910012958A KR1019890019309A KR890019309A KR910012958A KR 910012958 A KR910012958 A KR 910012958A KR 1019890019309 A KR1019890019309 A KR 1019890019309A KR 890019309 A KR890019309 A KR 890019309A KR 910012958 A KR910012958 A KR 910012958A
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KR
South Korea
Prior art keywords
interrupt
bus
requester
signal
interrupt bus
Prior art date
Application number
KR1019890019309A
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Korean (ko)
Other versions
KR920001815B1 (en
Inventor
박병관
강경용
심원세
기안도
윤남석
윤용호
권오건
박승규
Original Assignee
경상현
재단법인 한국전자통신연구소
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority to KR1019890019309A priority Critical patent/KR920001815B1/en
Publication of KR910012958A publication Critical patent/KR910012958A/en
Application granted granted Critical
Publication of KR920001815B1 publication Critical patent/KR920001815B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

내용 없음.No content.

Description

인터럽트 버스의 동기 방법How Interrupt Buses Are Synchronized

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 구성을 나타내는 블럭도,1 is a block diagram showing the configuration of the present invention;

제2도는 본 발명의 동작을 나타내는 프로우챠트.2 is a flowchart showing the operation of the present invention.

Claims (1)

다중처리기 시스템에서, 프로세서(1), (2)로 부터 인터럽트 요청을 받아 인터럽트 처리기(5), (6)로 요청하는 인터럽트 요청기(4)와, 인터럽트 요청기(4)의 요구에 따라 중재과정을 수행하여 그 결과를 인터럽트 요청기(4)로 보내거나 인터럽트의 발생을 처리하면서 그 결과를 프로세서(1), (2)로 알려주는 인터럽트 처리기(5), (6)와, 중재과정을 수행하는 인터럽트 아비터(7)와, 인터럽트 버스 클럭신호(IBCLK)를 생성하는 클럭 제너레이터(8)와, 인터럽트 버스 동기신호(IBSYNC)를 생성하거나 수신하는 인터럽트 버스 동기 신호 구동 및 수신기(9)와, 인터럽트가 전송되는 인터럽트 버스(3)와, 인터럽트 버스 클럭신호(IBLCK), 인터럽트 버스 동기신호(IBSYNC)라 각각 전송되는 신호선(6a), (6b)들로 구성하여 인더럽트를 수행중에는 인터럽트 버스 동기신호를 “참”으로 구동하면서, 수행이 완료되면 “거짓”으로 구동하도록 한 인터럽트 버스의 동기방법.In the multiprocessor system, an interrupt request is received from the processors 1 and 2, and the interrupt requester 4 requests the interrupt handlers 5 and 6 to arbitrate according to the request of the interrupt requester 4. The interrupt handlers (5) and (6), which send the result to the interrupt requester (4) or handle the occurrence of interrupts and inform the processor (1) and (2) of the result, An interrupt arbiter 7 to perform, a clock generator 8 for generating an interrupt bus clock signal IBCLK, an interrupt bus synchronization signal driver and receiver 9 for generating or receiving an interrupt bus synchronization signal IBSYNC, Interrupt bus (3), interrupt bus clock signal (IBLCK) and interrupt bus synchronization signal (IBSYNC), respectively, are composed of signal lines (6a) and (6b) to be transmitted. Drive sync signal to "true" A method of synchronizing an interrupt bus that, when done, drives it to "false". ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890019309A 1989-12-22 1989-12-22 Interrupt Bus Synchronization Method KR920001815B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890019309A KR920001815B1 (en) 1989-12-22 1989-12-22 Interrupt Bus Synchronization Method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890019309A KR920001815B1 (en) 1989-12-22 1989-12-22 Interrupt Bus Synchronization Method

Publications (2)

Publication Number Publication Date
KR910012958A true KR910012958A (en) 1991-08-08
KR920001815B1 KR920001815B1 (en) 1992-03-03

Family

ID=19293464

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890019309A KR920001815B1 (en) 1989-12-22 1989-12-22 Interrupt Bus Synchronization Method

Country Status (1)

Country Link
KR (1) KR920001815B1 (en)

Also Published As

Publication number Publication date
KR920001815B1 (en) 1992-03-03

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