KR910009792B1 - Facsimile Signal Processing Circuit - Google Patents

Abstract

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Description

Facsimile Signal Processing Circuit

1 is a conventional circuit diagram.

2 is a facsimile signal processing circuit diagram according to the present invention.

3 is a timing diagram of a CCD driving clock according to the present invention.

4 is a timing diagram of a RAM address signal and a read / write control signal according to the present invention.

5 is a timing diagram of a signal controlled by a period and software of? _TG according to the present invention, and a read period signal diagram outputted by them.

* Explanation of symbols for the main parts of the drawings

A: CCD sensor B: Clock generating circuit

C: light counter D: lead counter

E: Address selector F: Oagate

G: NAND gate H: Lead cycle decision circuit

I: D flip-flop J.K.M: endgate

L: Divider N: Video Processing Circuit

O: Serial input / serial output RAM P: Black / white counter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a facsimile signal control circuit, and in particular, processes a facsimile video signal into a binarized picture signal to switch control signal generation, binarization signal storage and output of a CCD (photoelectric converter) image sensor. The present invention relates to a sequence signal processing circuit adapted to be processed in series by means of.

Configuration of the sum signal control circuit in the conventional facsimile device as shown in FIG. 1, the main clock is applied to the CCD control clock generating circuit (1) controls clock _{(∮ TG, ∮ 1, ∮} 2, ∮ RS, ∮ _SH ) is generated and applied to the CCD unit 2, while the control clock ∮ _SH is applied to the video processing circuit 3 and the D flip-flop 4, respectively, and the shift register is transferred through the inverter I1. (5), the output V ₀ of the CCD unit 2 is applied to the input terminal D of the D flip-flop 4 via the video processing circuit 3, and its output Q is shifted. The register 5 and the sub CPU (central processing unit) 6 are configured to be applied to the main CPU 7.

Referring to the operation state of the conventional circuit configured as described above, the CCD control clock generation circuit 1 operated by the main clock is the control clock ( _TG , ∮ ₁ , ∮ ₂ , ∮ _RS , 필요한) necessary for driving the CCD unit 2. _SH ) is generated to drive the CCD image sensor, and the video signal A outputted to the output terminal V ₀ in response to the driving of the CCD unit 2 is applied to the video processing circuit 3 and binarized to the output terminal thereof. The output signal B is outputted.

This signal is again delayed to match the driving motive of the CCD unit 2 while passing through the D flip-flop (Δ) and input to the 8-bit shift register 5 to subtract the acknowledgment signal ACK every eight clocks. The sub CPU 6 reads the parallel output D of the shift register 5, converts the data into a suitable form, and then applies it to the main CPU 7.

In the conventional signal control circuit operated in this manner, the serial output signal of the CCD is binarized and then converted into parallel so that the CPU can process the signal. However, since the 2048 bit or 1728 bit must be processed and coded within at least 10 ms, While processing the signal, the CPU could not do anything else, so the sub-CPU was employed to process the signal. Therefore, the hardware part should be added, the sub CPU with high processing speed should be adopted, and the channel that can communicate with the CPU should be configured using RAM, which has a complicated structure and a large amount of software. .

The present invention is connected to a simple circuit in order to solve the above problems by varying the time to read the contents stored in the RAM according to the amount of black and white information of the video signal without loss regardless of the driving of the image sensor Invented to provide information to the CPU, which will be described in detail with reference to the accompanying drawings.

2 is a facsimile signal processing circuit diagram according to the present invention. As shown therein, a CCD sensor (A), a clock generating circuit (B), a write counter (C), a read counter (D), Address selector (E), O gate (F), NAND rate (G), read period determination circuit (H), D flip-flop (I), AND gate (JKM), divider (L), video processing circuit (N) ), The serial input / serial output RAM (O), the black / white counter (P), and the CPU are interconnected, and the operational effects of the present invention configured as described above will be described in detail with reference to the waveform diagrams of FIGS. 3 to 5. As follows.

In FIG. 2, the clock generation circuit B is composed of a clock generator for generating a clock required for driving a general CCD sensor A and a synchronization generator for synchronizing an internal circuit. The clock generator includes a counter, a flip-flop, It is composed of a gate and the like and its timing diagram is shown in FIG.

First, by the write counter clock signal 12 of the clock generating circuit B, the write counter C starts counting the dummy 32 bits 0 to 4096. The start of the count is after the start of the clock signal (∮ _TG ) and when the 4096th address is made, the write count completion signal 14 waits for the next cycle to generate the clock signal (∮ _TG ). Therefore, the write counter C can be activated so that the count can be started only by the clock signal ∮ _TG .

On the other hand, the read counter clock signal 9 from the clock generation circuit B is combined with the external control signal 10 at the ora gate F and applied to the read counter D. The read counter D is counted up by a switch, and this external signal is output high to the input of the NAND gate G only when the CPU is in a standby state. The clock of the read counter D can be input only in the case of the high H level indicating that the output of the read period determination circuit H is the read period.

The output of the read counter D indicates a storage address of the speech signal to be read by the CPU. On the other hand, the outputs of the write counter C and the read counter D are input to the A terminal and the B terminal of the address selector E, respectively, and the A terminal input or the B terminal input is selected by the selection signal 13. In addition, the selection signal 13 selectively outputs the highest address of the RAM by an exclusive OR circuit, with an output divided by two by one line read start signal 2.

On the other hand, the read / write signal 24 of the RAM has a high (H) state while the selection signal 13 is high (H), that is, when the read address is selected, the output of the address selector outputs the read address of the RAM. To keep it from being written to the memory, and when the select signal 13 is low (L), while the write address is output to the RAM as long as the select signal 13 enters into the low L period, the write address is written to the RAM. Makes it possible.

The input clock 9 of the read counter D, the input clock 12 of the write counter C, the address selection signal 13, the read / write signal 24, the write address 15, and the read address 16 ) Is shown in FIG.

The read signal period determining circuit H generates a signal indicating that the address output of the read counter D is an address of a valid speech signal. The signal 17 is cleared by clearing the flip-flop I at the completion of the valid address. Will be disabled. The signal 17 is changed to active high (H) by the write counter completion signal 14 when the write address reaches the final address (address 4096). In this state, when the clear signal 25 is applied from the CPU to the read counter D, the output signal of the read period determination circuit H becomes active high H and the output of the AND gate J becomes high H. Is changed. If the input signal 4 of the AND gate K is in the high H state, the output of the AND gate K is in the high H state, and the read period is maintained in the active high H state.

At this time, when the read OK signal 3 is inputted as high (H), the read counter D counts up, and when the input is inputted as low L, the input of the read counter D is counted down while maintaining the high (H) state. .

The initial start address value of the read counter D is loaded by the one-line read start signal 2, and the first address of the read period is started to be output to the address B output signal 16.

Therefore, when the read OK signal 3 continues to be high H, the read counter D counts 1728 times and keeps the output 5 of the AND gate K high during the period. In other words, the read OK signal 3 and the one-line read start signal 2 are given in software, and the two signals output the RAM address for 1728 dots and inform the CPU at the same time.

5 shows the read address clear signal 25, the single line read start signal 2, the read OK signal 3, the read start 4, the read period signal 5 and the CCD sensor A by the switch. _A timing diagram showing the relationship between the _TG outputs.

Here, the low speed time and the number of times of the read OK signal 3 are determined in software by the contents of the output data 23 of the black / white counter P and the B / W signal 22. In other words, when the output value 23 of the black / white counter P is small, the read OK signal 3 appears very much in a short period, but when the output value of the black / white counter P is large, it appears less in a long period.

As described in detail above, the present invention significantly reduces the CPU time required to process the black and white information of the binarized video signal depending on the software, thereby increasing the coding efficiency by the CPU, and Therefore, by varying the time to read the contents stored in RAM, it provides lossless information to the CPU regardless of the image sensor's operation, thereby maximizing the processing efficiency of the CPU to be suitable for variable length coding of the facsimile, and independent of the CPU. By independently writing and reading the talk signal, it is possible to provide a general talk signal control function that enables efficient management of the talk signal even in a hardware configuration employing any kind of CPU.

Claims (1)

The video signal output from the CCD sensor A by the clock signal of the clock generation circuit B is connected to the main CPU through the video processing circuit N, the serial input / serial output RAM O, and the black / white counter P. In the facsimile signal processing circuit applied to the write counter, the write counter C generates a write address according to the write clock signal of the clock generation circuit B and applies a write count completion signal to the clock generation circuit B. And a read counter (D) for generating a read address by the read clock signal of the clock generation circuit (B) under the control of the sub-CPU clearing, one-line read start, a read ok signal, and the like, and the clock generation circuit (B). An address selector E for selecting the write address of the write counter C or the read address of the read counter D and applying the read address of the write counter C to the serial input / serial output RAM O and the read counter (D A read period determination circuit H for generating a read period determination signal based on the read address signal of < RTI ID = 0.0 >), < / RTI > Oa gate F, which outputs G) and the output signal of the NAND gate G and the read clock signal of the clock generation circuit B, and applies them to the read counter D, and the read period determination circuit H. The flip-flop I, the output signal of the flip-flop I, and the read period determination circuit H, which receive the output signal of the " An AND gate (J) for supplying the read period determination signal of < RTI ID = 0.0 > and < / RTI > Pack characterized in that SIMI's speech signal processing circuit.

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