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KR910006980A - 멀티포트 메모리 - Google Patents

멀티포트 메모리 Download PDF

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Publication number
KR910006980A
KR910006980A KR1019900013984A KR900013984A KR910006980A KR 910006980 A KR910006980 A KR 910006980A KR 1019900013984 A KR1019900013984 A KR 1019900013984A KR 900013984 A KR900013984 A KR 900013984A KR 910006980 A KR910006980 A KR 910006980A
Authority
KR
South Korea
Prior art keywords
port
memory
sense amplifier
data register
memory cell
Prior art date
Application number
KR1019900013984A
Other languages
English (en)
Other versions
KR940006995B1 (ko
Inventor
신지 미야모토
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR910006980A publication Critical patent/KR910006980A/ko
Application granted granted Critical
Publication of KR940006995B1 publication Critical patent/KR940006995B1/ko

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

내용 없음

Description

멀티포트 메모리
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 멀티포트 메모리의 1실시예를 나타낸 회로도.

Claims (1)

  1. 복수의 메모리셀이 행렬형상으로 배열된 메모리셀 어레이와, 이 메모리셀 어레이의 메모리셀의 각 메모리셀이 접속되어 비트선의 전위변화를 검지하여 증폭·해치(增幅·Latch)시키는 센스엠프(20), 상기 비트선의 전위변화를 상기 센스앰프(20)에 고속으로 검지시키는 배리어 트랜지스터(T1, T2)를 갖추고 있는 RAM 포트와, 데이터 레지스터(30)와 주변회로로 이루어지고 컬럼방향의 시리얼 액세스기능을 갖고 있는 SAM 포트를 구비하고, 상기 RAM 포트의 메모리셀 어레이와 SAM 포트의 데이터 레지스터(30)간의 데이터전송을 전송게이트(TRG1, TRG2)를 통해서 행하는 멀티포트메모리에 잇어서, 상기 센스앰프(20)에 의해 증폭·래치된 비트선(BL10, BL10)의 전위가 상기 전송게이트(TRG1, TRG2)를 거쳐서 상기 데이터 레지스터(30)에 직접 전송되도록 접속시킨 것을 특징으로 하는 멀티포트메모리.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900013984A 1989-09-05 1990-09-05 멀티포트 메모리 KR940006995B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1-229799 1989-09-05
JP1229799A JP3061060B2 (ja) 1989-09-05 1989-09-05 マルチポートメモリ

Publications (2)

Publication Number Publication Date
KR910006980A true KR910006980A (ko) 1991-04-30
KR940006995B1 KR940006995B1 (ko) 1994-08-03

Family

ID=16897853

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900013984A KR940006995B1 (ko) 1989-09-05 1990-09-05 멀티포트 메모리

Country Status (3)

Country Link
US (1) US5138581A (ko)
JP (1) JP3061060B2 (ko)
KR (1) KR940006995B1 (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2664843B2 (ja) * 1992-09-22 1997-10-22 株式会社東芝 マルチポートメモリ
KR960006274B1 (ko) * 1993-11-17 1996-05-13 삼성전자주식회사 듀얼포트 메모리 장치
US5963485A (en) * 1998-08-19 1999-10-05 Stmicroelectronics, Inc. Method and apparatus for bit line recovery in dynamic random access memory

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5755592A (en) * 1980-09-18 1982-04-02 Nec Corp Memory device
JPS6072020A (ja) * 1983-09-29 1985-04-24 Nec Corp デュアルポ−トメモリ回路
US4931992B1 (en) * 1986-01-17 1998-03-03 Toshiba Kk Semiconductor memory having barrier transistors connected between sense and restore circuits
JPS62165787A (ja) * 1986-01-17 1987-07-22 Toshiba Corp 半導体記憶装置
JPS63261598A (ja) * 1987-04-20 1988-10-28 Hitachi Ltd 半導体メモリ
JP2694953B2 (ja) * 1987-11-25 1997-12-24 株式会社東芝 半導体記憶装置
JPH01224993A (ja) * 1988-03-04 1989-09-07 Nec Corp マルチポートメモリ

Also Published As

Publication number Publication date
JPH0393089A (ja) 1991-04-18
US5138581A (en) 1992-08-11
JP3061060B2 (ja) 2000-07-10
KR940006995B1 (ko) 1994-08-03

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