KR910005933B1 - Screen strobe control circuit - Google Patents

Abstract

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Description

Screen Strobe Control Circuit in Multi-Screen Generator

1 is a system applied to the present invention.

2 is a circuit diagram according to the present invention.

3 is a diagram illustrating a multi-screen configuration according to the present invention.

* Explanation of symbols for main parts of the drawings

100: keyboard 200: microcomputer unit

300: analog switch unit 400: analog / digital conversion unit

500: controller 600: dual port memory

700-900: 1-3 Digital / Analog Converter

1000: color encoder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-screen generator for television receivers and video tape recorders, and more particularly to a screen strobe control circuit in a multi-screen generator capable of varying screen strobes and strobe times.

In general, picture-in-picture (PIP) reduces the picture of the picture source from the main picture to 1/9 and inserts the picture into a predetermined part of the picture on the monitor so that the user can simultaneously display two pictures. I could see it. In another method, there is a multi-screen generator that displays two or more image sources on one monitor as a technology for viewing a plurality of screens as in the PIP.

In the conventional strobe function, when the strobe key is pressed, several screens appear in sequence at a predetermined time interval. That is, conventionally, when the strobe key is pressed whenever desired, the strobe function is executed, and the data in the small screen is fixed in units of one feed or one frame, and the strobe time cannot be changed.

Accordingly, an object of the present invention is to provide a circuit having a strobe function in a small screen generating image processing apparatus.

Another function of the present invention is to provide a circuit for varying the strobe time.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

신호와 라인(603)을 통해 출력되는 어드레스신호(AR)에 의해 상기 아나로그/디지털 변환부(400)에서 디지털화 비디오 신호를 다중화면의 윈도우에 따라 억세스포트인 어드레스 데이터라인(603, 602)을 통해 직렬포트를 지나 저장되고 독출의 상기 랜덤포트의 제어신호 억세스포트의 어드레스 신호에 의해 직렬 포트를 통해 출력되는 듀얼포트메모리부(600)와, 상기 콘트롤러부(500)의 D/A변환용 샘플링 클럭에 따라 상기 듀얼포트메모리부(600)로부터 출력된 디지털 데이터를 휘도 및 칼라신호별로 아나로그 신호로 변환하는 제1-3 디지털 / 아나로그 변환부(700 - 900)와, 상기 콘트롤러부(500)의 라인(509, 510)을 통해 출력되는 합성동기 신호의 페레스탈 클램프 및 자화면위치 결정신호에 의해 상기 제1-3디지탈/아나로그 변환부(700-900)의 디지털신호를 라인(1001)을 통해 입력된 주화면 비디오 신호와 엔코딩하여 다중화면을 발생하는 칼라 엔코더부(1000)로 구성된다.1 is a system block diagram to be applied to the present invention, a multi-screen by checking a keyboard unit 100 for inputting a command according to a user's multi-screen mode setting, and a multi-screen processing command of the keyboard unit 100. The processing clock and data are generated through the lines 201 and 202 and are generated from the microcomputer 200 which checks the data output state from the data check line 203, and a video signal synchronization separator (not shown). The vertical and horizontal synchronization signals of the main screen and the small screen through the lines 503-506 and receive the first and second reference frequencies from the oscillator through the lines 501 and 502 and output them through the microcomputer 200. According to the vertical and horizontal synchronization signals of the small screen, the data from the main screen is digitalized to the multi-screen source of the small screen, which is different from each other. The controller 500 and the controller are configured to control the display to be read according to the vertical and horizontal synchronization signals of the main screen when the small screen is inserted into the main screen, and to display the multiple screens on the monitor by analogizing the read data. The luminance Y and the color RY, input through the lines 301-303 by the luminance Y and color (BY, RY) selection switching signals output through the lines 304-306 of the part 500. Outputs the analog switch unit 300 and ANA → Y → Y → BY → Y → Y → sequentially and outputs the output of the analog switch unit 300 to the controller unit 500. The analog / digital converter 400 converts the digital data by the sampling signal of the A / D conversion clock terminal CLK, and has two input / output terminals, which can be independently accessed from both ports. The controller unit 500 lines 605-608 according to the screen vertical and horizontal synchronization signals. A random port and outputting through

The analog / digital converting unit 400 accesses the address data lines 603 and 602, which are access ports, according to a window of a multi-screen, by the signal and the address signal AR output through the line 603. The dual port memory unit 600 and the controller 500 which are stored after passing through the serial port and output through the serial port by the address signal of the control signal access port of the random port. A first to third digital / analog converters 700 to 900 for converting digital data output from the dual port memory unit 600 into analog signals according to luminance and color signals according to a clock, and the controller 500 The digital signal of the first to third digital / analog converters 700 to 900 is converted to a line 1001 by a perestal clamp and a sub picture positioning signal of the synthetic synchronous signal outputted through the lines 509 and 510 of FIG. )Through And a color encoder 1000 for generating a multi-screen by encoding the input main screen video signal.

FIG. 2 is a circuit diagram according to the present invention and receives screen selections (1, 2, 4) and function selection information data output to the line 201 of the microcomputer 200 of FIG. 1 through the data input terminal S-IN. The shift register 110 receives the signal output to the line 202 to the club input terminal (MIC-CLK) and shifts the serial data of the data input terminal (S-IN) and outputs it as 7-bit parallel data, and the micom unit ( The data check signal output to the line 203 of the line 200 is received by the data check stage MIC-STB and counted according to the clock of the reference clock stage 2fsc: fsc = 3.539545 MHz to output the shift register 110. A first counter 120 for controlling the level of the signal to be converted into pulses, and the predetermined parallel output data of the shift register 110 is latched according to the input clock signal of the data check terminal MIC-STB, and then the first counter 120 is controlled. The parallel by the reset by the output of the two counter 120 The first latch circuit 130 generates a signal having a predetermined pulse width and outputs a signal having a predetermined pulse width, and supplies the output signal as a clock signal for selecting a screen and a function, and a predetermined output of the shift register 110 to a data test stage (MIC-STB). Latches the input clock signal by the clock signal inverted by the inverter 150 and generates a signal having a predetermined pulse width by the output of the second counter 120 to generate a clock signal for controlling the strobe mode. A second latch circuit 155 for latching a predetermined output level of the third latch circuit 155 and the shift register 110 by a clock signal of the data check terminal MIC-STB to set a strobe rising and falling mode. ) And a multiplexer 160 that selects and loads a strobe setting value inputted to the first to third lines 161 to 163 according to the information input of the four screens and input to the first to third lines 161 to 163 according to the output of the second latch circuit 140. ) And the second latch circuit 140 The rising / falling counting mode is set by the output, and the output of the third latch circuit 155 is clocked to raise and lower the strobe level according to the set rising and falling counting modes. A third counter 180 counting by the second counter, a second counter 170 counting the small screen vertical synchronization signal inputted to the line SVS to a predetermined value, and an output and a third output of the second counter 170. The decoder 190 which decodes the output of the counter 180 to determine a desired strobe time and the setting mode of the four screens are designated, and the output of the third counter 180 is counted according to the output of the decoder 190. A fourth counter 108 to be selected by the multiplexer 160 via lines 1-3 through 161-163 to set the strobe loading value, and the corresponding output of the corresponding output of the decoder 190. Clearing the second counter 170 A selection unit 109 which is selected according to the inverter 153 and the output of the decoder 190 and controls a screen strobe according to counting with the 2-bit conversion of the dual port memory unit 600 through lines D6 and D7. It is composed of

3 is a diagram illustrating a multi-screen configuration according to the present invention.

Based on the above configuration, a specific embodiment of the present invention will be described in detail with reference to 1, 2, and 3, when the user presses the strobe up or down key to change the strobe time through the keyboard unit 100. . When the pressed key input is processed by the microcomputer 200 and input to the controller 500, the address bus AR of the dual port memory unit 600 is processed by processing a strobe function and a variable command input to the controller 500. Controls strobe function according to key input by conversion of upper 2 bits of. The process according to the strobe function in the controller unit 500 will be described in detail with reference to FIG. 2. The data input terminal of the shift register 110 converts serial data of the screen selection and function selection information through the microcomputer unit line 201. It is output as 7 bits in parallel by shifting according to the clock inputted to (S-IN) and inputted to the clock input terminal (MIC-CLK).

The data inspection signal output through the line 203 of the microcomputer 200 is received by the data inspection stage MIC-STB and down counted according to the clock of the reference clock stage 2fc. Inputs the signal of the STB to the clocks of the 1-2 latch circuits 130 and 140, latches the output data of the shift register 110, and converts the signal of the data check terminal MIC-STB into an inverter. Inverted at 150 and input to the clock terminal of the third latch circuit 155, the predetermined output of the shift register 110 is latched. At this time, when the counting value of the first counter 120 reaches a predetermined value, the first and third latch circuits 130 and 155 are cleared, and the latched level is dropped to the low level 'first latch circuit 130. (Bito-bit4) signal of the output terminal (Bito-bit4) as the clock for screen and function selection, and the signal of the output terminal (bit6) of the third latch circuit 155 is input to the clock of the third counter 180 to be clocked in the strobe mode. Used as In order to set the strobe conversion level according to the output of the second latch circuit 140, the multiplexer 160 automatically sets the intermediate value 6 of the first line 161 before pressing the strobe up and down keys. Selecting and counting the up / down of the third counter 180 according to the output of the second latch circuit 140.

For example, when the output of the output terminal Bit5 of the second latch circuit 140 is low, the third counter 180 is set to the down counting mode to down count the value loaded by the multiplexer 160. That is, when 6, 5 → 4 → 3 →. The first counter is down counted to 1 and input to the decoder 190, and when the output of the output terminal Bit5 of the second latch circuit 140 is high, the third counter 180 is set to an up counting mode and up counted.

That is, when 6, 6 → 7 → 8... Counting up to 11 and inputting to the decoder 190 to input the value of 6 loaded from the multiplexer 160 to the fourth counter 108 and inputting the signal according to the four screen selection to the line 165 to count Run The second counter 170 counts up to 110 small picture vertical synchronization signals input to the line 171 to the decoder 190 as the output of the third counter 180. The decoder 190 determines the desired strobe time. The output of the third counter 180 is 7, and the second counter 180 is the same as when the output of the third counter 180 is 6 and the output of the second counter 170 is 60. The output of the 170 is 70, the output of the third counter 180 is 8 and the output of the second counter 170 is 80 or. When the time is variable, the corresponding output of the decoder 190 becomes “high” and the count value of the fourth counter 108 is rotated so that the multiplexer 160 is connected through the 1-3 lines 161 to 163. The second counter 170 is cleared through the inverter 153 and input as a clock of the selector 109 to convert the values of the output lines D6 and D7 of the selector 109.

The output lines D6 and D7 of the selector 109 correspond to the upper two bits of the address bus AR of the dual port memory unit 600 of FIG. 1 and may be 00 → 01 according to the output of the decoder 190. Change it to → 10 → 11, switch to the position to be written according to the monitor setting window, and change the moving timing.

Referring to the above-described embodiment according to the small screen generation position of FIG. 3, when the strobe time variable mode is entered, in the case of one of the small screens, the first default value θ is small during the (θ> 0) small screen vertical synchronization signal (Vsync). The screen is moved and the small screen is stopped for the next θ small screen vertical synchronization signals (Vsync).

When the strobe time-down signal is input from the microcomputer unit 200, the small screen moves for the next Ved minus (ed) V minus d (d> 0) V syncs from the initial default value θ Vsyncs and the next (ed) Vsyncs. During sync, the small screen is stopped. Subsequently, when the strobe time down count control signal is received, the operation may be repeated by subtracting d Vsyncs for each down signal input from the current repetition period.

When the strobe time-up signal comes in, the operation may be repeated in the current repetition period plus d syncs. While the initial default value is θ Vsync, the small screen moves only the position of (1) in FIG. 3 and the small screen of the positions of (2), (3), and (4) stops. During the next θ V syncs, the child screen at position (2) moves and the screens at positions (1), (2), and (3) become stationary. During the next θ V syncs, the small screen at position (3) is moved, and the small screens at positions (1), (2) and (4) are stopped. During the next θ V syncs, the small screen at position (4) moves and the child screen at position (1) (2) (3) is stopped.

The above operation is repeated repeatedly. When the strobe time-down coral comes in, the previously described operation is repeated for the remaining V sync minus d V syncs in the current cycle. Whenever the down signal is input, the repeating operation is repeated by subtracting d syncs from the current repetition period, and when the strobe time up signal is received, the previous operation is repeated by adding d syncs from the current repetition period.

As described above, by setting the n strobe (n> 0) strobe section of the strobe, each time the user presses the up and down keys, the n value is changed to easily move each sub screen during the setting value set to n. There is an advantage that the moving time can be changed according to the user's preference.

Claims (1)

In the strobe control circuit in the multi-screen generator having the micom unit 200, the controller unit 500, and the dual port memory unit 600, the screen selection output to the line 201 of the microcomputer unit 200 ( 1,2,4) and function selection information data received at the data input terminal S-IN, and a signal outputted at the line 202 is received at the clock input terminal MIC-CLK, and directly connected to the data input terminal S-IN. A shift register 110 for outputting 7-bit parallel data and a data check signal output to the line 203 of the microcomputer 200 to the test stage MIC-STB. a first counter 120 and a predetermined parallel output data of the shift register 110 for controlling a predetermined count according to a clock of fsc = 3.439545MHz) to convert the level of the output signal of the shift register 110 into a pulse. In accordance with the input clock signal of the data check stage (MIC-STB0) The first latch circuit 130 which generates a signal having a predetermined pulse width with the parallel output data level by reset by the output of the second counter 120 after being latched, and supplies it as a clock signal for selecting a screen and a function. And latching the predetermined output of the shift register 110 by the clock signal inverted by the inverter 150 by the input clock signal of the data inspecting terminal MIC-STB and then by the output of the second counter 120. The third latch circuit 155 which generates a signal having a predetermined pulse width to generate a clock signal for strobe mode control, and the predetermined output level of the shift register 110 are clocked by the data check terminal MIC-STB. The second latch circuit 140 which latches by the signal and sets the strobe rising and falling modes, and is selected according to the information input of the four screens, and the first to third lines according to the output of the second latch circuit 140. 161-163) to input the strobe setting The multiplexer 160 which selects and loads the rising / falling counting mode is set by the output of the second latch circuit 140 so that the output of the third latch circuit 155 is clocked. A third counter 180 that counts the output of the subfield by raising and lowering the strobe level according to the set rising and falling counting modes, and a second counting signal of the small screen vertical synchronization signal input to the line SVS0 to a predetermined value. A counter 170, a decoder 190 for decoding the output of the second count 170 and the output of the third counter 180 to determine a desired strobe time, and a setting mode of the four screens, The output of the three counters 180 is counted and loaded according to the output of the decoder 190 to be selected by the far flexure 160 through the line 1-3 lines 161-163 with the setting of the strobe loading value. The fourth counter 108, The inverter 153 for clearing the second counter 170 of the corresponding output of the coder 190 is selected according to the output of the decoder 190 and the dual port memory unit 600 through the lines D6 and D7. And a selection unit (109) for controlling the screen strobe according to the counting with the 2-bit conversion.

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