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KR910005629A - Time switch device - Google Patents

Time switch device Download PDF

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Publication number
KR910005629A
KR910005629A KR1019890012182A KR890012182A KR910005629A KR 910005629 A KR910005629 A KR 910005629A KR 1019890012182 A KR1019890012182 A KR 1019890012182A KR 890012182 A KR890012182 A KR 890012182A KR 910005629 A KR910005629 A KR 910005629A
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South Korea
Prior art keywords
data
memory means
call
demultiplexer
time slot
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KR1019890012182A
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Korean (ko)
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KR920005064B1 (en
Inventor
오돈성
강구홍
박권철
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경상현
재단법인 한국전자통신연구소
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Publication of KR910005629A publication Critical patent/KR910005629A/en
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Publication of KR920005064B1 publication Critical patent/KR920005064B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/08—Time only switching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1316—Service observation, testing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13393—Time slot switching, T-stage, time slot interchanging, TSI

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Monitoring And Testing Of Exchanges (AREA)

Abstract

내용 없음No content

Description

타임 스위치 장치Time switch device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 구성을 나타낸 블럭도.1 is a block diagram showing the configuration of the present invention.

제2도는 통화 메모리부와 제어부 간의 개략적인 연결 구조도.2 is a schematic connection structure diagram between a call memory unit and a control unit.

Claims (8)

가입자 측의 서브하웨이로 부터 차동통화 데이터 신호를 입력하여 이를 병렬 데이터로 멀티플렉싱하여 출력하는 멜티플렉서(1), 통화 메모리수단과 제어메모리 수단을 구비하여 상기 멀티플렉서(1)로 부터 전송된 병렬 데이터를 시스템 클럭의 제어하에 상기 통화 메모리 수단으로 순차 쓰기를 행한 후 다시 상기 통화메모리 수단으로 부터 랜덤 읽기를 수행하여 타임슬롯 교환을 하고, 상기 제어 메모리 수단은 타임스위치 프로세서(TSP)로 부터 데이타를 받아 상기 통화 메모리 수단으로 보내며, 상기 데이터는 상기 통화 메모리 수단의 읽기 어드레스로서 사용되는 제1타임슬롯 교환유니트(2), 상기 제1타임 슬롯 교환유니트(2)로 부터 받은 병렬 데이터를 차동 병렬 데이터로 변환하여 출력하는 제1데이터 링크 인터페이스 유니트(3), 상기 제1타임 슬롯 교환유니트(2)로 부터 받은 톤(tone), R2, DTMF 신호, 인트러졍터(intra junctor) 및 녹음안내/회의통화 등의 서비스 신호를 차동병렬 데이터로 출력하는 디멀티플렉서(4), 상기 디멀티플렉서(4)로 부터 인트러 졍터용 신호를 받아들이고 데이터 링크 측으로 부터 서비스 신호를 입력하여 멀티플렉싱하여 병렬 데이터를 출력하는 멀티플렉서(5), 데이터 링크로 부터 받은 차동 병렬 데이터를 병렬 데이타로 변환하여 출력하는 제2데이터 링크 인터페이스 유니트(6), 상기 제2데이터 링크 인터페이스 유니트(6)에 연결되어 상기 제1타임슬롯 교환유니트(3)와 동일한 기능을 하는 제2타임 슬롯 교환유니트(7), 상기 제2타임슬롯 교환유니트(7)로 부터 받은 병렬 데이터를 디멀티플렉싱하여 차동병렬 데이터러 가입자측에 출력하는 디멀플렉서(8), 및 상기 각 유니트 상태 및 통화로 상태를 시험하고 유지보수하기 위한 시험 및 유지보수 유니트로 구성된 것을 특징으로 하는 타임스위치 장치.A parallel transmission transmitted from the multiplexer (1) having a multiplexer (1) for inputting a differential call data signal from a subscriber sub-way and multiplexing it into parallel data, and outputting a call memory means and a control memory means; Write data sequentially to the call memory means under the control of a system clock, and then perform random reads from the call memory means to exchange timeslots, and the control memory means reads data from a time switch processor (TSP). The parallel data received from the first time slot exchange unit 2 and the first time slot exchange unit 2 used as a read address of the call memory means, and the data are transmitted to the call memory means. First data link interface unit (3) for converting the data into a first time slot Demultiplexer (4), the demultiplexer (4) for outputting service signals such as tone, R2, DTMF signal from the ring unit (2), intra junctor and recording guide / conference call as differential parallel data A multiplexer (5) which receives the signal for the interceptor from 4) and inputs and multiplexes the service signal from the data link side, and outputs the parallel data; and a second which converts the differential parallel data received from the data link into parallel data and outputs the parallel data. A second time slot exchange unit 7 and a second time slot connected to a data link interface unit 6 and the second data link interface unit 6 and functioning the same as the first time slot exchange unit 3. The demultiplexer 8 demultiplexes the parallel data received from the slot exchange unit 7 and outputs the demultiplexer 8 to the differential parallel data subscriber. Time switch device, characterized in that consisting of testing and maintenance unit for testing and maintenance of the state to. 제1항에 있어서, 상기 멀티플레서(1)는 32채널로 이루어진 128서브하이웨이로 부터 차동 통화 데이터 2.048Mbps 신호를 받아들여 8비트 병렬 데이터 8.192Mbps 신호로 멀티플렉싱하는 것을 특징으로 하는 타임스위치 장치.The time switch device according to claim 1, wherein the multiplexer (1) receives a differential call data 2.048 Mbps signal from a 128 sub-highway consisting of 32 channels and multiplexes the signal into an 8-bit parallel data 8.192 Mbps signal. 제1항에 있어서, 상기 제1 및 제2타임슬롯 교환 유니트(2,7)의 통화 메모리 수단은 이중 포트 SRAM으로 구성된 것을 특징으로 하는 타임 스위치 장치.2. The time switch device according to claim 1, wherein the communication memory means of the first and second timeslot exchange units (2, 7) are constituted by a dual port SRAM. 제1항에 있어서, 상기 디멀티플렉서(8)는 상기 제2타임슬롯 교환유니트(7)로 부터 타임슬롯 교환이 이루어진 8.192Mbps의 8비트 병렬 데이터를 입력하여 디멀티플레싱한후 2.048Mbsd의 차동통화 데이터 형태로 128개의 서브하이웨이를 통해 출력하는 것을 특징으로 하는 타임 스위치 장치.2. The demultiplexer (8) according to claim 1, wherein the demultiplexer (8) is 2.048 Mbsd differential call data after demultiplexing and inputting 8.192 Mbps of 8-bit parallel data in which timeslot exchange is performed from the second timeslot exchange unit (7). Time switch device, characterized in that output through the 128 sub-highway in the form. 제1항에 있어서, 상기 제1 및 제2타임슬롯 교환 유니트(2,7)의 통화 메모리 수단에서의 순차 쓰기 어드레서를 행하기 위한 어드레스 번지를 할당하는 시스템 클릭은 8.192MHz 인것을 특징으로 하는 타임 스위치 장치.2. The system click according to claim 1, characterized in that the system click for assigning an address address for sequential write addressing in the call memory means of said first and second timeslot switching units (2, 7) is 8.192 MHz. Time switch device. 제1항에 있어서, 상기 제1데이터 링크 인터페이스 유니트(3) 및 상기 디멀티플렉서(4)를 통해서 출력되는 데이터는 8.192Mbps의 차동데이터로 각각 1024 타임 슬롯씩 출력하는 것을 특징으로 하는 타임 스위치 장치.2. The time switch device according to claim 1, wherein the data outputted through the first data link interface unit (3) and the demultiplexer (4) are output by 1024 time slots as 8.192 Mbps differential data, respectively. 제1항에 있어서, 상기 제1타임 슬롯 교환유니트(2)의 제어메모리 수단은 2K용량의 메모리로 되었고, 통화 메모리 수단은 2K용량의 4개의 이중포트 SRAM으로 구성된 것을 특징으로 하는 타임 스위치 장치.2. The time switch device according to claim 1, wherein the control memory means of the first time slot exchange unit (2) is a memory of 2K capacity, and the call memory means is composed of four dual port SRAMs of 2K capacity. 제1항에 있어서, 상기 제2타임 슬롯 교환유니트(7)의 제어 메모리 수단은 2K용량의 2개 메모리로 구성되었고, 통화 메모리 수단은 2K 용량의 4개의 이중 포트 SRAM으로 구성되었으며, 하나의 제어 메모리가 2개의 통화 메모리의 읽기 어드레스를 지정해주고, 읽혀진 2개의 통화 메모리 출력이 하나의 디멀티플렉서(8)에 함께 연결되도록 구성된 것을 특징으로 하는 타임 스위치 장치.2. The control memory means of the second time slot exchange unit (7) according to claim 1, wherein the control memory means of the second time slot exchange unit (7) consists of two memories of 2K capacity, the call memory means of the four dual port SRAMs of 2K capacity, and one control. A memory designating a read address of two call memories, and the read two call memory outputs being configured to be connected together to one demultiplexer (8). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890012182A 1989-08-26 1989-08-26 Time switch device KR920005064B1 (en)

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KR1019890012182A KR920005064B1 (en) 1989-08-26 1989-08-26 Time switch device

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KR1019890012182A KR920005064B1 (en) 1989-08-26 1989-08-26 Time switch device

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KR920005064B1 KR920005064B1 (en) 1992-06-26

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020036051A (en) * 2000-11-07 2002-05-16 박종섭 Time switching board using 5×5 matrix
KR100339463B1 (en) * 1996-02-06 2002-07-18 포만 제프리 엘 Parallel on-the-fly processing of fixed length cells
KR100703508B1 (en) * 2001-02-28 2007-04-03 삼성전자주식회사 Digital exchange system with digital time switch

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100339463B1 (en) * 1996-02-06 2002-07-18 포만 제프리 엘 Parallel on-the-fly processing of fixed length cells
KR20020036051A (en) * 2000-11-07 2002-05-16 박종섭 Time switching board using 5×5 matrix
KR100703508B1 (en) * 2001-02-28 2007-04-03 삼성전자주식회사 Digital exchange system with digital time switch

Also Published As

Publication number Publication date
KR920005064B1 (en) 1992-06-26

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