KR910004203B1 - Pwm signal generator of digital method using digital carrier generator - Google Patents

Abstract

No content.

Description

Digital PWM Signal Generator Using Digital Carrier Generator

1 is a block diagram illustrating a PWM signal generator according to the prior art.

2 is a block diagram of a digital PWM signal generator using a digital carrier generator according to the present invention.

3 is a detailed block diagram of the digital carrier generator shown in FIG.

4 is an explanatory diagram of the operation of the digital carrier generator of FIG.

* Explanation of symbols for main parts of the drawings

1: digital calculator 6, 7, 20: comparator

8, 9: NAND gate 10: Digital Carrier Generator

11, 70: flip-flop 12: counter logic circuit

13: counter flip-flop 30: inverter gate

40, 50, 60: NOR gate

The present invention relates to a digital PWM signal generator, and more particularly, to a digital PWM signal generator using a digital carrier generator.

The conventional digital pulse width modulation (PWM) signal generator counts until the PWM signal becomes " 1 " after the counter start command signal is generated, as shown in FIG. PWM signal generator A comprising a counter 3 and an inverter gate 4 and an AND gate 5 that count until the counter 2 and the PWM signal become " 0 ", and the PWM signal generator A It consists of a digital calculator (1) which applies two count values to the "

The clock CP is generated at a constant cycle, and the counter start command signal is generated once every N clocks to start the counters 2 and 3.

The conventional PWM signal generator A configured as described above operates as follows.

The counters (2) and (3) decrement the counting every clock from the counter value, which is the output value of the digital calculator 1, according to the start command signal of the counter. It will remain stopped until it arrives. However, the counter completion signal output from the counters 2 and 3 becomes "0" during counting and "1" during stop.

(MAX〉V〉MIN)식으로 PWM 신호가 "1"값을 갖도록 해야 한다.In addition, assuming that the calculation result of the digital calculator 1 is the maximum value MAX so that the PWM signal is always "1", and the calculation result of the digital calculator 1 is the minimum value MIN so that it is always "0", When the calculation result value of the digital calculator 1 is V

The PWM signal should have a value of "1" in the form of (MAX>V> MIN).

That is, the counter 2 is a counter that counts until the PWM signal becomes "1" after the counter start command signal is generated, and the counter 3 is again "" after the counter start command signal is generated. A counter that counts until 0 "is used. Whenever the counter start command signal is generated, a period in which the PWM signal is" 1 "occurs due to the difference in the counter value applied to the counter 3, and the PWM signal is generated once every N clocks. Done.

의 비율동안 PWM 신호가 '1"이 되도록 하기 위해서는 카운터(2), (3)에 인가되는 카운터 값의 차를 D라 하면,

식으로하여 N개의 클록에 대해

값의 비율을 얻을 수 있다. 따라서 카운터(2)에 인가되는 카운터값을

, 카운터(3)에 인가되는 카운터값을

라 하면 D 만큼의 카운터값의 차이를 얻게되어 PWM 신호는

의 비율동안 "1"값을 갖게 되는 것이다.Formula

D is the difference between the counter values applied to the counters (2) and (3) so that the PWM signal becomes '1' during the ratio of

So for N clocks

You can get the ratio of the values. Therefore, the counter value applied to the counter 2

, The counter value applied to the counter (3)

In other words, you get the difference of D counter value.

It will have a value of "1" during the ratio of.

로 변환하여 그 신호발생기에 인가하여야 한다(단,

이와같은 종래의 변환과정은 PWM 신호발생기(A)의 구조에 의해 발생되는 것으로서 디지틀 계산기(1)이 계산시간에 이 변환시간이 추가되어 디지틀 계산기(1)의 처리속도가 늦어지는 문제점이 있었다.In order to generate the PWM signal, the calculation result (V) of the digital calculator (1) cannot be directly applied to the PWM signal generator (A).

To be applied to the signal generator (

Such a conventional conversion process is generated by the structure of the PWM signal generator A, which has a problem in that the digital calculator 1 adds this conversion time to the calculation time, thereby slowing down the processing speed of the digital calculator 1.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and provides a digital PWM signal generator using a digital carrier generator to directly apply the calculation result of the digital calculator to the PWM signal generator without processing for conversion. It is. Hereinafter, the present invention will be described in detail with reference to FIGS. 2 to 4.

2 is a block diagram illustrating the overall circuit configuration of a digital PWM signal generator using a digital carrier generator according to the present invention.

을 "0"으로 하는 비교기(20)와, 상기 비교기(20)의 출력

와 상기 디지틀 캐리어발생기(10)에서 출력된 증감신호를 입력으로 하는 제1NOR 게이트(40)와, 상기 비교기(20)의 출력

이 인버터어 게이트(30)를 통하여 발생된 신호와 플립플롭(70)의 출력을 입력으로 하는 제2NOR 게이트(50)와, 상기 제1, 2 NOR게이트(40), (50)의 출력을 입력으로 하는 제3NOR 게이트(60)와, 상기 제3NOR 게이트(60)의 출력을 입력으로 하는 플립플롭(70)으로 구성된다.2, a digital carrier for outputting a digital carrier for increasing / decreasing repeatedly from a predetermined minimum value MIN to a maximum value MAX, and an increase or decrease signal indicating whether the digital carrier is in an increased or decreased state. These two inputs (A) and (B) are inputted with the carrier generator 10, the digital carrier output from the digital carrier digital carrier generator 10, and the calculation result (V) signals from the digital calculator (1). Output when same)

Comparator 20, where " 0 " and the output of comparator 20

And a first NOR gate 40 which receives the increase and decrease signal output from the digital carrier generator 10 and the output of the comparator 20.

Inputs the second NOR gate 50 for inputting the signal generated through the inverter gate 30 and the output of the flip-flop 70, and the outputs of the first and second NOR gates 40, 50. The third NOR gate 60 may be configured to be a flip-flop 70 having an output of the third NOR gate 60.

3 is a detailed block diagram of the digital carrier generator 10 shown in FIG.

은 "0"으로 되어 NAND 게이트(8)의 출력이 "1"로 된다. 다음 클록에 의해서는 증가/감소 카운터(B)의 카운터 현재값이 최대값이 되고 플립플롭(15)의 출력은 '1"(감소상태)로 되어 카운터 논리회로(12)의 출력인 카운터 다음값이 최대값-1이 되며, 이때 비교기(6)의 출력

은 "1"이 되어 플립플롭(11)의 입력이 현재의 출력값인 "1"이 NAND게이트(8), (9)을 거쳐 되돌아온다.In the drawing, if the output of the flip-flop 11 is " 0 " As a result, the maximum value -1, which is in an incremented state, is prepared, and this value is set back to the counter present value by the counter CP by the clock CP. That is, since the present counter value is increased as the maximum value -1, the next value of the counter becomes the maximum value MAX. At this time, the two inputs of the comparator 6 are the same, so the output

Becomes "0" and the output of the NAND gate 8 becomes "1". By the next clock, the counter present value of the increment / decrement counter B becomes the maximum value, and the output of the flip-flop 15 becomes '1' (decrement state), and the next value of the counter which is the output of the counter logic circuit 12. Is the maximum value -1, where the output of the comparator 6

Becomes " 1 ", and the input of the flip-flop 11 returns the current output value " 1 " via the NAND gates 8 and 9;

The counter present value at the next clock becomes the maximum value -1, and the output of the flip-flop 11 continues with "1" and remains in a reduced state.

이 "0"으로되어 NAND 게이트(8), (9)를 거쳐 플립플롭(15)의 입력이 "0"으로 된다.If the present counter value reaches the minimum value +1 by repeating this operation, the next value of the counter becomes the minimum value and the outputs of the comparators 6 and 7 are output.

This becomes "0" and the input of the flip-flop 15 becomes "0" through the NAND gates 8 and 9.

In addition, by the next clock, the counter present value becomes the minimum value, and the output of the flip-flop 11 becomes "0" (increase state). In other words, the next value of the counter becomes the minimum value +1 and the output of the comparator 7 becomes " 1 " and the increment operation continues until the maximum value is reached again.

Referring to the operation explanatory diagram of the digital carrier generator 10 of FIG. 4 by the repetitive operation as described above, the counter present value is continuously increased / decreased between the minimum value MIN and the maximum value MAX, and flip-flop. The increase / decrease signal which is the output of (11) becomes " 0 " when the digital carrier increases and " 1 " when the digital carrier increases.

One period of the digital carrier generator 10 having such a signal form is (MAX-MIN) × 2. Here, if the digital calculator with the PWM signal always "1" is applied to the digital carrier generator 10 with the calculation result value as the maximum value MAX and the calculation result value with the PWM signal always "0" as the minimum value MIN, respectively, The digital carrier output from the digital carrier generator 10 increases / decreases the range from the minimum value to the maximum value, and the period becomes (MAX-MIN) × 2.

이 "0"이 되며, 따라서 인버어터(30)와 제1, 2, 3 NOR 게이트(40), (50), (60)를 통해 입력된 플립플롭(70)이 다음 클록에서 "1"로 출력된다. 이때의 상기 디지틀 캐리어 발생기(10)에서 출력된 디지틀캐리어는 V_-1로 진행하여 비교기(20)의 출력이 "1"이 되고, 플립플롭(70)의 입력은 현재의 출력인 "1"이 제2, 3 NOR 게이트 (50), (60)를 거쳐 되돌아온다. 이 출력상태로 디지틀 캐리어가 최소값까지 진행하고 다시 증가상태(증감신호는 "0"이다)로 되어 V의 값이 될 때까지 유지하게 된다. 또한 증가상태에서 디지틀 캐리어가 V의 값이 되면 비교기(20)의 출력

은 "0"이 됨과 동시에 인버어터게이트(30)를 통해 제2NOR 게이트에 입력되어 출력이 "0"이 되고, 그에 따라 제1, 2NOR 게이트의 출력은 각각 "1", "0"이 된다. 다음 클록에서는 디지틀 캐리어의 값이 V₊₁로 되어 비교기(20)의 출력

이 "1"로 되며, 그에 따라 플립플롭의 출력은 "0"으로 된다. 즉, 상기 비교기(20)의 출력

이 "1"로 되었으므로 플립플롭(7)의 다음값은 현재출력인 "0"이 제2, 3NOR 게이트(50), (60)를 통해 되돌아오게 된다.Therefore, if the current calculation result V of the digital calculator 1 is applied to the comparator 24, the digital carrier reducer outputted from the digital generator 10 (in this case, the increase and decrease signal is "1") is the digital carrier value. Output of the comparator 20 when it is equal to the calculation result value V of the calculator 1

Becomes "0", so that the flip-flop 70 input through the inverter 30 and the first, second, and third NOR gates 40, 50, and 60 goes to "1" on the next clock. Is output. At this time, the digital carrier output from the digital carrier generator 10 proceeds to V _{−1 so} that the output of the comparator 20 is “1”, and the input of the flip-flop 70 is “1” which is the current output. It returns via the 2nd, 3 NOR gates 50 and 60. FIG. In this output state, the digital carrier advances to the minimum value, and increases to the incremental state (increase and decrease signal is "0") and is maintained until the value of V is reached. In addition, when the digital carrier becomes the value of V in the increasing state, the output of the comparator 20

Becomes "0" and is input to the second NOR gate through the inverter gate 30 so that the output becomes "0". Accordingly, the outputs of the first and second NOR gates become "1" and "0", respectively. At the next clock, the value of the digital carrier becomes V ₊₁ and the output of the comparator 20

Is " 1 ", so that the output of the flip flop is " 0 ". That is, the output of the comparator 20

Since the value of " 1 " is set to " 1 ", the next value of the flip-flop 7 returns the current output " 0 "

으로 된다. 이것은 디지틀 계산기(1)의 계산결과치(V)값은 PWM 신호가 "1"이어야 하는 비율과 같은 것이다.As a result of the repetition of this operation, the period in which the PWM signal is "1" becomes (V-MIN) x 2 every cycle by the digital carrier output from the digital carrier generator 10, and thus the period in which the PWM signal is "1" for the entire period. The ratio is

Becomes This is the calculation result (V) value of the digital calculator 1 is equal to the ratio at which the PWM signal should be "1".

As described above, the digital PWM signal generator using the digital carrier generator according to the present invention does not require a calculation process for converting the calculation result V of the digital calculator into a value suitable for a conventional PWM signal generator. As the processing speed of the digital calculator is not only high, but the maximum value and the minimum value can be determined according to the use, the frequency of the modulated signal is adjusted only by adjusting the clock frequency, so the effect that is not greatly restricted by the application range can be expected. have.

Claims (1)

In the digital PWM signal generator, a digital carrier which repeatedly increases / decreases from a predetermined minimum value (MIN) to a maximum value (MAX) and an increase / decrease signal indicating whether the digital carrier is in an increased or decreased state. The two inputs (A), the digital carrier generator 10 serving as an output, the digital carrier output from the digital carrier generator 10 and the calculation result value (V) signals from the digital calculator 1 are input. Output when (B) is equal

Digital PWM generator using a digital carrier generator, characterized in that consisting of a comparator (20) to "0".

Images