KR910000550B1 - Digital image signal processing system for multi-screen displaying - Google Patents

Abstract

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Description

Digital video signal processing circuit and method

1 is a block diagram according to the present invention.

2 is a detailed circuit diagram of a digital image signal processing circuit for multi-screen display of FIG. 1 according to the present invention.

* Explanation of symbols for main parts of the drawings

100,200: 1st, 2nd tuner 300,400: 1st, 2nd video signal source device

500: image signal processing circuit 600: display unit

700: keyboard

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image processing circuit, and in particular, converts an image signal into digital data, maps and stores the image signal in a frame memory by timing control, reads out a control signal, and simultaneously displays multiple images on one screen. Digital image signal processing circuit and method.

In general, in order to combine two or more different video signals into one new video signal, the signal level and synchronization signal of each video signal must be matched with each other. Are all different and do not match.

Therefore, in order to create a new video signal by combining different video signals, a controller for synchronizing the synchronization signal and the signal level was needed. Conventionally, for this purpose, there was a product in which a controller was built to have a multi-screen function in a TV or a VTR product, but it was expensive, and its function was limited to the product itself, which has been inconvenient in use.

Therefore, an object of the present invention is to separate the multi-screen function into a separate function without the built-in VTR or TV, and to configure the system universally, and to connect to this unit when there are two or more signal sources such as a TV or VTR. The present invention provides a method of realizing a multi-screen without editing a screen and modifying an existing TV or VTR.

It is still another object of the present invention to realize multiple screens by adjusting the timing of the memory time and the playback time of the synchronization signal phases of two different video signals in the frame memory using a method of mapping multiple image signals to a frame. In providing a circuit.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 13 is a circuit diagram according to the present invention, and includes a first and second tuners 100 and 200 for receiving a signal transmitted from a broadcasting station as a plurality of broadcast signals through an antenna ANT, which is a TV broadcast signal input terminal, and supplying the signals to two video signal sources. First and second video signal sources 300 and 400 for supplying an external video signal from a VTR or other TV video medium to a video signal source, and the first and second tuners 100 and 200 and the first and second video signal sources. A video signal processing circuit 500 for controlling 4 different video signals of 300 and 400 to be output to one screen at the same time, and a display unit 600 capable of displaying the output of the video signal processing circuit 500. And a keyboard 700 that can control the image processing circuit 500 by receiving a user key input.

Briefly describing an embodiment of the present invention according to the above configuration, video and audio signals transmitted from broadcasting stations are input through predetermined channels differently selected from the first and second tuners 100 and 200, and the first and second video signal source devices. When a predetermined video signal and an audio signal are input to the video signal processing circuit 500 from a VTR or another TV video medium of 300 or 400, the audio signal to be output is selected under the control of the keyboard 700 and the video signal processing circuit 500 Multiplexes the video signal input to the device, demodulates it into color, converts it into digital data, and stores it in the frame memory.

When the sync (vertical and horizontal) signals are separated from the video signals and input to the memory control signal generator, the write / read addresses of the frame memory are sequentially assigned according to the signals to access the image data for each field.

In this case, multiple screens are mapped and edited in the frame memory according to the write / read addresses. When the edited screen is converted into an analog signal and outputted to the display unit 800 in synchronization, multiple screens can be simultaneously viewed on the screen.

FIG. 2 is a detailed circuit diagram of the image signal processing circuit 500 of FIG. 1 according to the present invention, and includes a divider 1 for distributing an input RF signal and a video and audio input differently for each broadcasting station distributed from the divider 1. A first and second tuners 100 and 200 for receiving a signal and a first and second tuners 100 and 200 connected to the first and second tuners 100 and 200 so as to detect and output a video VIF and an audio SIF from a signal output therefrom; 2VIF and SIF detection circuits 4 and 5, a system controller 25 connected to the user-set keyboard 700 of FIG. 1 to receive a key input and generating a system control signal, and the first and second of FIG. A system controller connected to the video signal source devices 300 and 400 and receiving an audio signal from the first and second VIF and SIF detection circuits 4 and 5 and receiving key input from the keyboard 700. The first 4/1 ana to select and output the desired audio signal according to the control signal of 25). The multiplexer 24, the detection video signal of the first, second VIF, and SIF detection circuits 4 and 5 and the video signal of the first and second video signal source devices 300 and 400 are received by a control signal. Vertical and horizontal synchronizing from the video signals selected by the second and third 4/1 analog multiplexers 6 and 23 for selecting and outputting a video signal; and the second and third 4/1 analog multiplexers 6 and 23. Red-brightness (RY) and blue-brightness (R) from the first and second synchronous separation circuits (8 and 21) and the video signals selected by the second and third 4/1 analog multiplexers (6 and 23) to be separately outputted. BY) and output color signals of the first and second color signal demodulation circuits 7, 22 and the first and second color signal demodulation circuits 7 and 22 for demodulating and outputting the color of the luminance Y. When the first and second analog / digital converters 9 and 20 and the output digital signals of the first and second analog / digital converters 9 and 20 convert to digital signals of a predetermined bit, one field is written. The first field First and second video frame memories 10 and 19 for storing one-frame video digital data, and the second, third quarter analog multiplexer 6, according to the control of the system controller 25. Control the selection stage 23 to output a selection signal to select a desired video signal input from the first and second VIF and SIF detection circuits 4 and 5 and the first and second video signal source devices 300 and 400. Receives the vertical and horizontal synchronization signals of the first and second synchronization circuits 8 and 21 and generates sampling signals according to the digital data conversion of the first and second analog / digital converters 9 and 20. Memory control signal generation signal 17 for controlling write / read addresses and control signals of video frame memories 10 and 19 to construct multiple images by mapping first and second video frame memories 10 and 19 to generation signals. And output digital images of the mapped multiple images of the first and second video frame memories 10 and 19. First and second digital to analog converters 11 and 18 for converting data into analog signals, and the first and second digital / analog converters to an output selection control signal of the memory control signal generating circuit 17. 4 and 6 2/1 analog multiplexers 12, 15 and 16 for mixing the video signals output for each of RY and BY of 11 and 18, and RY output from the 4 2/1 analog multiplexer 12. Synchronization generated by the memory control signal generation circuit 17 by receiving the signal and the BY signal output from the fifth 2/1 analog multiplexer 15 and the Y signal output from the sixth 2/1 analog multiplexer 16. A color encoder 13 modulated with a combined video signal and outputted together with a signal, a buffer 14 for level shifting and buffering a composite video video signal of the color encoder 13 and outputting the modified multi-screen; Of the first 4/1 analog multiplexer 24 under the control of the controller 25; An audio amplifier 26 for amplifying and outputting a selective output audio signal, a composite video signal of the color encoder 13 and an audio signal of the first multiplexer 24 and modulating the audio signal of 3CH or 4CH RF modulator 27 is composed. In FIG. 2, the configuration of the display unit 600 of FIG. 1 connected to the buffer 14, the RF modulator 27, and the audio amplifier 26 is omitted.

In the above configuration, the 1-6 2/1 analog multiplexers 24, 6, 23, 12, 15, and 16 output 4 inputs (4/1), or the inputs 1 output (2/4). It is an analog multiplexer, and each device is a circuit known as a TTL device.

That is, the RF signal is input to the second tuners 100 and 200 through the divider 1, and the VIF and SIF signals output from the first and second tuners 100 and 200 are converted into the first, second VIF, and SIF detection circuits 4,. 5), and are input from the video A and B (VIDEO A, VIDEO B) and the first and second video signal source devices 300 and 400 reproduced by the first and second VIF and SIF detection circuits 4 and 5. Video 1 and 2 (VIDEO1, VIDEO2) are input to the 1-3-4 / 1 analog multiplexers 6, 23 and 24, and are output from the second and third 4/1 analog multiplexers 6 and 23. The video I and II signals are applied to the first and second color signal demodulation circuits 7 and 22 and the first and second synchronous separation circuits 8 and 21.

The RY, BY, Y signals output from the first color signal demodulation circuit 7 are connected to be input to the first analog-to-digital converter 9 to be converted into 8 bits, and the RY, BY, Y signals are converted into first bits. The RY, BY, and Y data input as data of the video frame memory 10 and output from the video frame memory 10 are input to the first digital-analog converter 11 to be analog signals of RY, BY, and Y. The RY, BY, and Y signals converted to the analog are input to the input terminals of the 4-6 2/1 analog multiplexers 12, 15 and 16.

The RY, BY, Y signal output from the second color signal demodulation circuit 22 is input to the input terminal of the second analog / digital converter 20, and the RY, BY, Y signal converted into 8 bits is the first video. The RY, BY, and Y data input as data of the frame memory 19 and output from the second video frame memory 19 are input to the second digital-to-analog converter 18, where RY, BY, and Y The RY, BY, and Y signals, which are converted into analog signals and converted into analog signals, are input to the input terminals of the 4-6 2/1 analog multiplexers 12, 15, and 16.

The outputs of the 4-6 2/1 analog multiplexers 12, 15, and 16 are input to the color encoder 13, and the composite image signal output from the color encoder 13 is transferred to the buffer 14. And is configured to be the final video output.

The audio (A), audio (B), and audio (4) and audio (2) signals output from the first, second VIF, and SIF detection circuits (4) (5) are first 4/1 analog multiplexers (24). Is inputted to the audio output from the first 4/1 analog multiplexer 24, and is input to the audio amplifier 26 to be the final audio output.

An input key signal input from the keyboard 700, which is an external control key, is input to the system controller 25, and the audio selection signal 4 input from the system controller 25 is the first 4/1 analog multiplexer 24. The memory control signal C is input to the memory control signal generation circuit 17. The read / write (R / W), chip selector (CS) and address signals (a) and (b) generated by the memory control signal generation circuit 17 are first and second video frame memories 10 and 19. Real / Wirte (R / W), chip selector (CS) and address signals of the video selection signal (e) are controlled by the second, third and fourth analog multiplexers (6) and (23). It is input by signal. The output video selection signal (G) output from the memory control signal generation circuit 17 is input as a control signal of the 4-6 2/1 analog multiplexer 12, 15, 16, and generates a memory control signal. The reproduced video signal synchronizing signal (H) generated by the circuit 17 is input as a synchronizing signal of the color encoder 13.

The clock signals CK1 (child) and CK2 (car) generated by the memory control signal generation circuit 17 are sampled according to the conversion from the analog signals of the first and second analog / digital converters 9 and 20 to digital data. It is input to the clock.

The video (I) signal is input to the first synchronous separation circuit 8, and the horizontal (H) synchronous and vertical (V) synchronous signals are separated and input to the memory control signal generation circuit 17, and the video (II) signal is The vertical and horizontal synchronous signals inputted to the second synchronous separation circuit 21 are separated to be input to the memory control signal generation circuit 17, and the composite image signal (ta) output from the color encoder 13 is Input to the RF modulator 27, the output RF signal of the RF modulator 27 is configured to be output to the outside.

Therefore, a specific embodiment of the present invention will be described in detail with reference to FIG. 2, and the RF input signal is distributed by the distributor 1 and input to the first and second tuners 100 and 200 so that a desired TV broadcast can be made according to channel selection. To be selected and played back through video (A), video (B) and audio (1), audio (2) via first, second VIF and SIF detection circuits (4, 5) and video (1), video (2) and Audio (1) and audio (2) are input to the 1-3-4 / 1 analog multiplexer (6) (23) (24) to control signals of the system control (25) and memory control signal generation circuit (17). The video I and the video II are selected from the second and third 4/1 analog multiplexers 6 and 23 and the first and second video signals from the first 4/1 multiplexer 24 are selected. Audio (1, 2) and audio (A, B) output from the original device (300, 400) and the first and second VIF and SIF detection circuits (4, 5) are selected.

The audio output signal is output to the outside via the circuit of the audio amplifier 26, and the video (I) signal is demodulated by the RY, BY, and Y signals by the first color signal demodulation circuit 7 to thereby obtain a first analog signal. The digital signal is converted into a digital signal by the / digital converter 9 and stored in the first video frame memory 10.

The video (II) signal is demodulated into RY, BY, and Y signals by the second color signal demodulation circuit 22 and converted into a digital signal by the second analog / digital converter 20 to generate a second video frame memory 19 Remembered).

When the video (I) and video (II) signals are stored in the first and second video frame memories 10 and 19, the horizontal (H) sync signal and the vertical (V) sync signal and video of the video (I) are stored. The memory read address is generated in the memory control signal generation circuit 17 in accordance with the horizontal (H) sync signal and the vertical (V) sync signal in (II). In the first and second video frame memories 10 and 19, video signals of one frame of the video I and the video II are stored, and a control signal is generated so that the 2nd field is read out when the 1st field is written. Do not disconnect the video signal.

The image control signal to be expressed is input from the system controller 25 to the memory control signal generation circuit 17, and the first and second video frame memories 10 and 19 are transmitted from the memory control signal generation circuit 17 according to the control signal. The memory mapping can be controlled by using the write and read addresses of).

The video signal edited with multiple images is input to the first and second digital-to-analog converters 11 and 18 to be converted into an analog signal, and the video (I) and video (II) signals are 4-6 2 /. 1 Analog multiplexer 12, 15, 16 are mixed into RY, BY, and Y signals, respectively, modulated into composite video signal by color encoder 13, and then level shifted and buffered through output buffer 14. It is output as a composite video signal transformed into.

The modified multi-screen video signal is modulated by the RF modulator 27 to be output as a 3CH or 4CH RF signal. In this case, if the terminal device to be connected is a video monitor, the video signal and audio output signal can be used for screen playback and audio playback. If the terminal device to be connected is a color TV, the 3CH or 4CH TV signal from the RF modulator 27 can be used for video and audio. The audio signal can be reproduced.

As described above, the existing digital video processor is partially mounted inside the VTR or color TV, and is configured as a dedicated circuit. However, in the present invention, a digital video processor is generally used to be connected to a general TV, a video monitor, a VTR, etc. Can produce

Accordingly, even if a separate circuit configuration is not installed in a TV, a VTR, a video monitor, or the like, there is an advantage in that a multi-screen can be edited and displayed in a desired form when watching TV broadcast or playing a VTR video signal.

Claims (2)

A digital image processing circuit comprising: a divider (1) for distributing an input RF signal, first and second tuners (100,200) for receiving video and audio signals differently input for each broadcasting station distributed from the divider (1), and First and second VIF and SIF detection circuits 4 and 5 connected to the first and second tuners 100 and 200 to detect and output the video VIF and the audio SIF from the signals output therefrom; The system controller 25 is connected to the user set keyboard 700 of FIG. 1 to generate a system control signal by receiving a key input, and is connected to the first and second video signal source devices 300 and 400 of FIG. And receiving the audio signal output from the first, second VIF, and SIF detection circuits 4 and 5 to select and output a desired audio signal according to the control signal of the system controller 25 which has received the key input of the keyboard 700. Detection of the first 4/1 analog multiplexer 24 and the first, second VIF and SIF Second and third 4/1 analog multiplexers for receiving the detected video signal of the circuits 4 and 5 and the video signals of the first and second video signal source devices 300 and 400 to select and output a desired audio signal according to a control signal. (6,23), and first and second synchronous separation circuits (8,21) for separating and outputting vertical and horizontal synchronization from the video signal selected by the second and third 4/1 analog multiplexers (6,23); And demodulating and outputting colors of red-luminance (RY), blue-luminance (BY), and luminance (Y) from the video signal selected by the second, third, 4/1 analog multiplexers 6,23. First and second analog / digital converters for converting the two color signal demodulation circuits 7 and 22 and the output color signals of the first and second color signal demodulation circuits 7 and 22 into digital signals of predetermined bits. (9,20) and a 1-frame video digit by taking a second field when the output digital signal of the first and second analog / digital converters (9,20) is written one field. The first and second video frame memories 10 and 19 storing data and the selection stages of the second and third quarter analog multiplexers 6 and 23 are controlled by the control of the system controller 25. The first and second synchronous separation circuit 8 outputs a selection signal for selecting a desired video signal input from the first and second VIF and SIF detection circuits 4 and 5 and the first and second video signal source devices 300 and 400. Receiving the vertical and horizontal synchronization signals of the first and second analog / digital converters 9 and 20 and generating sampling signals according to the conversion of the digital data of the first and second analog / digital converters 9 and 20, respectively. A memory control signal generation signal 17 for controlling write / read addresses and control signals of the first and second video frame memories 10 and 19 to generate multiple images by mapping the generated signals to the first and second video frame memories 10 and 19; First to convert the output digital data of the mapped multiple images of the video frame memories (10, 19) into analog signals; The RY, BY, and Y of the first and second digital / analog converters 11 and 18 to the output selection control signal of the two digital / analog converters 11 and 18 and the memory control signal generating circuit 17. 4-6 2/1 analog multiplexers 12, 15 and 16 for mixing the output video signal, and RY signal and 5 2/1 analog output from the 4 2/1 analog multiplexer 12 The BY signal output from the multiplexer 15 and the Y signal output from the sixth 2/1 analog multiplexer 16 are received and modulated into a composite video signal in combination with the synchronization signal generated by the memory control signal generation circuit 17. A color encoder 13 to be output, a buffer 14 for level shifting and buffering the composite video video signal of the color encoder 13 and outputting the modified multi-screen; and according to the control of the system controller 25 Amplify and output the selected output audio signal of the first 4/1 analog multiplexer 24 Is composed of an audio amplifier 26, an RF modulator 27 for modulating the composite video signal of the color encoder 13 and the audio signal of the first multiplexer 24 and modulating the audio signal of 3CH and 4CH. A digital video signal processing circuit for multi-screen display. In the multi-screen display method, two TV broadcast video signal sources and two or more first and second video signal sources provided from the outside are input, and are included in the TV broadcast video signal sources and the first and second video signal sources. Separating the synchronization signal, multiplexing the respective video signal sources, demodulating them in color, and digitizing them, and mapping the digitalized video data into multiple screens on a field-by-field basis in a storage area for a frame according to the detected synchronization signal. A digital video signal processing method comprising converting a video signal edited by being mapped to a screen into an analog signal, mixing and modulating the video signal into a composite video signal to display a multi-screen.

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